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Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.


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Patent
16 Apr 2008
TL;DR: In this article, an NMOS transistor 14 having one end connected to one end of a resistance memory element 10 is provided, and when a voltage is applied to the resistor element 10 via the NMOS transistors 14 to switch the resistor memory element from the low resistance state to the high resistance state, the gate voltage of the transistor 14 is set at a value which is equal to or greater than the total of the reset voltage and the threshold voltage.
Abstract: An NMOS transistor 14 having one end connected to one end of a resistance memory element 10 is provided, and when a voltage is applied to the resistance memory element 10 via the NMOS transistor 14 to switch the resistance memory element 10 from the low resistance state to the high resistance state, the gate voltage of the NMOS transistor 14 is set at a value which is equal to or greater than the total of the reset voltage of the resistance memory element 10 and the threshold voltage of the NMOS transistor 14 and is smaller than the total of the set voltage of the resistance memory element 10 and the threshold voltage of the NMOS transistor 14, whereby the voltage applied to the resistance memory element 10 is set at a value which is equal to or greater than the reset voltage and is smaller than the set voltage.

41 citations

Journal ArticleDOI
TL;DR: In this article, a new grooved-gate MOSFET with its drain separated from channel implanted regions (DSC structure) is proposed for the purpose of obtaining higher breakdown voltages: drain sustaining voltage and highest applicable voltage placed by hot-carrier effects.
Abstract: A new grooved-gate MOSFET with its drain separated from channel implanted regions (DSC structure) is proposed for the purpose of obtaining higher breakdown voltages: drain sustaining voltage and highest applicable voltage placed by hot-carrier effects. Nonimplanted regions between channel implanted and source/drain regions are a unique feature of this device structure. The self-aligned nonimplanted region in the channel is obtained by using silicon dioxide and resist overhangs. These overhangs are fabricated by grooving the silicon substrate. The DSC structure helps reduce the electric field at the drain. Characteristics of experimental devices are presented and compared with those of conventional MOSFET's, from the viewpoint of overall VLSI device design. This device structure is shown to provide remarkable improvements, achieving a 3- or 4-V increase in drain sustaining voltage, as well as a 1- or 2-V increase in the highest applicable voltage as limited by hot-electron injection. In addition, the proposed device can alleviate such short-channel effects as V th lowering, and in particular, diminish narrow-channel effects. The influence of nonimplanted length on breakdown voltage is also clarified using the CADDET, two-dimensional analysis program.

41 citations

Patent
William E. Ham1
27 Dec 1976
TL;DR: In this article, the leakage current and threshold voltage of a field effect transistor on an insulator substrate, at both room temperature and after operation at relatively high temperatures (150° C), are substantially reduced by selectively doping edge regions adjacent the transverse side surfaces of the channel region of the FET.
Abstract: Instabilities in the leakage current and threshold voltage of a field effect transistor on an insulator substrate, at both room temperature and after operation at relatively high temperatures (150° C), are substantially reduced by selectively doping edge regions adjacent the transverse side surfaces of the channel region of the field effect transistor, wherein the breakdown voltage of the channel-to-drain junction is substantially increased Atoms are placed in these edge regions to provide therein a carrier concentration of at least 5 × 10 16 atoms-cm -3 of the opposite conductivity type to that of the source and drain regions The doped edge region extends partly across said channel region and extends fully across the side surface at the end of the source region

41 citations

Patent
30 Nov 1990
TL;DR: An insulated gate transistor as mentioned in this paper consists of a semiconductor region which is provided so as to be in contact with the channel regions and has the same conductivity type as that of the channel region and has an impurity concentration higher than that of channel region.
Abstract: An insulated gate transistor comprises source regions; drain regions; channel regions provided between the source and drain regions; a gate electrode; and gate insulative film provided between the channel regions and the gate electrode. The device has a semiconductor region which is provided so as to be in contact with the channel regions and has the same conductivity type as that of the channel region and has an impurity concentration higher than that of the channel region. The gate electrode has at least two opposite portions which face each other.

41 citations

Journal ArticleDOI
TL;DR: In this paper, a sub-100-nm vertical MOSFET with high pressure oxide growing at source/drain (S/D) regions to reduce the gate overlapped capacitances and threshold voltage adjustment with a doped APCVD film is presented.
Abstract: Sub-100-nm vertical MOSFET has been developed for fabrication with low cost processing. This is the first vertical MOSFET design that combines 1) a vertical L/sub DD/ structure processed with implantation and diffusion steps, 2) high-pressure oxide growing at source/drain (S/D) regions to reduce the gate overlapped capacitances, and 3) threshold voltage adjustment with a doped APCVD film. The drive current per unit channel width and S/D punch-through voltage are higher than that of previously published vertical MOSFETs. Fabrication processes are well established, and equipment of the 1 /spl mu/m CMOS generation can be used to fabricate sub-100-nm channel length MOSFETs with good electrical characteristics and high performance.

41 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202330
202279
202161
202055
201958
201845