Topic
Drain-induced barrier lowering
About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.
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08 Feb 2006TL;DR: In this article, the authors proposed an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate, and a monitor unit for monitoring at least one of the drain currents of the plurality of mOSFeters.
Abstract: Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current. The monitor unit includes a constant current source and a monitoring MOSFET formed on the same substrate as the plurality of MOSFETs, the substrate voltage regulating unit includes a comparison unit for comparing the source potential of the monitoring MOSFET with a predetermined reference potential with the drain terminal of the monitoring MOSFET and the drain terminals of the plurality of MOSFETs connected to the ground potential, and substrate voltage regulating unit feeds back the output voltage output based on the comparison result by the comparison unit to the substrate voltage of the monitoring MOSFET.
40 citations
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01 Oct 2002TL;DR: The asymmetric channel region can include silicon abutting the source region and a heterostructure material such as Si1-xGex extending to and abutding the drain region.
Abstract: A MOSFET semiconductor device having an asymmetric channel region between the source region and the drain region. In one embodiment, the device comprises a mesa structure on a silicon substrate with the source region being in the substrate and the mesa structure extending from the source region and substrate. The asymmetric channel region can include silicon abutting the source region and a heterostructure material such as Si1-xGex extending to and abutting the drain region. The mole fraction of Ge can increase towards the drain region either uniformly or in steps. In one embodiment, the doping profile of the channel region is non-uniform with higher doping near the source region and lower doping near the drain region.
40 citations
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16 Aug 2002
TL;DR: In this paper, an integrated circuit fabricated in a single silicon substrate includes a high-voltage output transistor having source and drain regions separated by a channel region, and a gate disposed over the channel region.
Abstract: An integrated circuit fabricated in a single silicon substrate includes a high-voltage output transistor having source and drain regions separated by a channel region, and a gate disposed over the channel region. Also included is an offline transistor having source and drain regions separated by a channel region and a gate disposed over the channel region of the offline transistor. A drain electrode is commonly coupled to the drain region of the high-voltage output transistor and to the drain region of the offline transistor.
40 citations
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TL;DR: In this article, a drain current model for surrounding gate MOSFETs was developed using a quasi-two-dimensional cylindrical form of the Poisson equation and based on the drift-diffusion equation.
Abstract: In this paper we present a complete and analytical drain current model for surrounding gate MOSFETs. The model was developed using a quasi-two-dimensional cylindrical form of the Poisson equation and based on the drift-diffusion equation. The model applicable for digital/analog circuit simulation contains the following advanced features: precise description of the subthreshold, near threshold and above-threshold regions of operation by one single expression; single-piece drain current equation smoothly continuous from the linear region to the saturation region; considering the source/drain resistance; inclusion of important short channel effects such as velocity saturation, drain-induced barrier lowering and channel length modulation.
40 citations
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IBM1
TL;DR: In this article, a multiple-gate FinFET is defined, where the channel region comprises the middle portion of a fin structure and the source and drain regions comprise end portions of the fin structure.
Abstract: Disclosed is a multiple-gate transistor that includes a channel region and source and drain regions at ends of the channel region. A gate oxide is positioned between a logic gate and the channel region and a first insulator is formed between a floating gate and the channel region. The first insulator is thicker than the gate oxide. The floating gate is electrically insulated from other structures. Also, a second insulator is positioned between a programming gate and the floating gate. Voltage in the logic gate causes the transistor to switch on and off, while stored charge in the floating gate adjusts the threshold voltage of the transistor. The transistor can comprise a fin-type field effect transistor (FinFET), where the channel region comprises the middle portion of a fin structure and the source and drain regions comprise end portions of the fin structure.
40 citations