Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Method for manufacturing self-aligned thin film transistor

Abstract: Disclosed is a method for manufacturing a self-aligned metal oxide thin film transistor. According to the present invention, a metal oxide semiconductor layer having a high carrier concentration is formed, and then a channel region which is self-aligned with a gate electrode is oxidized by a plasma having oxidbillity so that the channel region has a low carrier concentration and the source and drain regions have high carrier concentrations while the resulting transistor has a self-aligned structure. In addition, the threshold voltage of the transistor is controlled by the conditions under which the channel region of the transistor is subsequently oxidized by plasma having oxidbillity at a low temperature. Therefore, the controllability of the characteristics of the transistor is improved significantly, and the manufacturing process is simplified.

Optimum design of n + -n - double-diffused drain MOSFET to reduce hot-carrier emission

Abstract: Channel electric field reduction using an n+-n-double-diffused drain MOS transistor to suppress hot-carrier emission is investigated. The double-diffused structure consists of a deep low-concentration P region and a shallow high-concentration As region. The channel electric field strongly depends on such process and device parameters as the length of the n-diffusion region, drain junction depth, gate oxide thickness, gate length, applied voltage, and P implant energy. The optimum condition for a double-diffused structure is determined based on those parameter dependences of the channel electric field. The results of the optimum drain impurity profile to give the minimum channel electric field are obtained when the maximum lateral electric field is located at the boundary between the P region and the As region. The hot-carrier immunity of MOSFET and test circuits are improved by two orders of magnitude and one order of magnitude, respectively, under the optimum conditions.

A Two-Dimensional Gate Threshold Voltage Model for a Heterojunction SOI-Tunnel FET With Oxide/Source Overlap

Abstract: A two-dimensional (2D) analytical gate threshold voltage model for a heterojunction silicon-on-insulator tunnel field-effect transistor structure with gate oxide overlap is developed. The infinite series method, with suitable boundary conditions, is used to solve the 2D Poisson’s equation for surface potential. The surface potential is used to develop the expression for the proposed analytical threshold voltage in closed form. Developed threshold voltage is verified for different gate length, drain voltage, oxide thickness, and gate dielectric materials against Synopsys Technology Computer-Aided Design numerical simulation results and found to predict the simulated results accurately.

Method of forming isolation regions in a MOS transistor device

Abstract: The present invention is directed to a MOS transistor and its method of fabrication. The transistor includes isolating layers below source/drain regions of the transistor. In this manner, lateral diffusion occurring in the source/drain regions can be retarded. Accordingly, the fabricated. MOS transistor has the advantages of shallow junction depth, low junction capacitance, and better punchthrough resistance. Furthermore, since the bulk of the MOS transistor might be connected to a constant voltage, most likely ground, via a contact region, the floating body effects typically encountered in SOI (silicon-on-insulator) devices can be avoided.