Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Field effect transistor containing a wide band gap semiconductor material in a drain

Abstract: A field effect transistor comprising a silicon containing body is provided. After formation of a gate dielectric, gate electrode, and a first gate spacer, a drain side trench is formed and filled with a wide band gap semiconductor material. Optionally, a source side trench may be formed and filled with a silicon germanium alloy to enhance an on-current of the field effect transistor. Halo implantation and source and drain ion implantation are performed to form various doped regions. Since the wide band gap semiconductor material as a wider band gap than that of silicon, impact ionization is reduced due to the use of the wide band gap semiconductor material in the drain, and consequently, a breakdown voltage of the field effect transistor is increased compared to transistors employing silicon in the drain region.

Self-Aligned U-Gate Carbon Nanotube Field-Effect Transistor with Extremely Small Parasitic Capacitance and Drain-Induced Barrier Lowering

Abstract: A novel self-aligned U-gate structure for carbon nanotube (CNT) field-effect transistors (FETs) is introduced and shown to yield excellent dc properties and high reproducibility that are comparable with that of the best CNT FETs based on the previously developed self-aligned device structures. In particular the subthreshold swing of the U-gate FET is 75 mV/dec and the drain-induced barrier lowering is effectively zero, indicating that the electrostatic potential of the whole CNT channel is most efficiently controlled by the U-gate and that the CNT device is a well-behaved FET. Moreover the high-frequency response of the U-gate FET is investigated, and the parasitic capacitance of the device is measured and shown to be one magnitude smaller than that of the previously developed self-aligned device structures. Direct frequency domain measurements show that the U-gate CNT FETs can operate up to 800 MHz, which is also higher than previously reported values. The large improvement in the device high-frequency behavior is largely due to the replacement of the high-κ dielectric material between the source/drain and the gate by a vacant space with κ ≈ 1, and the significant reduction in the device parasitic capacitance renders the U-gate CNT FETs promising for rf applications.

Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect

Abstract: We report on negative capacitance (NC) FinFETs with ferroelectric Hf 0.5 Zr 0.5 O 2 (HZO) as gate dielectric on fully depleted silicon on insulator (FDSOI) substrate with various channel length (L CH ) of 450 nm to 30 nm and multiple fin widths (W FIN ) of 200 nm to 30 nm. We demonstrate all signature characteristics expected from NCFET: nearly hysteresis free operation (~3 mV), D and to the best of our knowledge, for the first time in Si MOSFETs, negative Drain Induced Barrier Lowering (DIBL) and Negative Differential Resistance (NDR). Remarkably, we observe significant improvement in the short channel effect compared to control FinFETs: both SS and DIBL are substantially lower for the NCFET for the same L ch /W Fin ratio. Importantly, these benefits become increasingly larger for shorter channel lengths.

Multiple operating voltage vertical replacement-gate (VRG) transistor

Abstract: An architecture for creating multiple operating voltage MOSFETs. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second spaced-apart doped regions formed in the surface. A third doped region forming a channel of different conductivity type than the first region is positioned over the first region. A fourth doped region of a different conductivity and forming a channel is positioned over the second region. The process of creating the gate structure for each of the two transistors allows for the formation of oxide layers of different thickness between the two transistors. The transistors are therefore capable of operating at different operating voltages (including different threshold voltages). Each transistor further includes fifth and sixth layers positioned respectively over the third and fourth regions and having an opposite conductivity type with respect to the third and fourth regions. In an associated method of manufacturing the semiconductor device, a first and second source/drain regions are formed in a semiconductor layer. A first field-effect transistor gate region, including a channel and a gate electrode is formed over the first source drain region and a second field-effect transistor gate region is formed over the second source/drain region. Fifth and sixth source/drain regions are then formed for each of the first and second field-effect transistors and further having the appropriate conductivity type. Variable thickness gate oxides are created by appropriately masking, etching, and regrowing gate oxides. As a result, the formed transistors operate at different operating voltages. Thus a plurality of such transistors operating at different operating voltage (as a function of the gate oxide thickness) can be formed in an integrated circuit.

Threshold voltage compensating circuits for fets

Abstract: A field effect semiconductor device including a plurality of field effect semiconductor elements formed on a common substrate and a compensating circuit for controlling the threshold voltage of said transistors by comparing the threshold voltage of one transistor to a reference voltage and generating a backward bias control voltage across a PN-junction of the one transistor between the source thereof, which is connected to the source of at least one of the other transistors, and the common substrate.