Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Semiconductor device for improved power conversion having a hexagonal-system single-crystal silicon carbide

Abstract: To provide a field-effect transistor having a large power conversion capacity and its fabrication method by decreasing the leakage current between the source and the drain of a semiconductor device made of hexagonal-system silicon carbide when the gate voltage of the semiconductor device is turned off and also decreasing the electrical resistance of the semiconductor device when the gate voltage of the semiconductor device is turned on. The main current path of the field-effect transistor is formed so that the current flowing between the source and the drain of, for example, a field-effect transistor flows in the direction parallel with the {0001} plane and a channel forming plane is parallel with the {1120} plane. Selected Drawing!FIG. 1

Process for manufacturing MOS Transistors having elevated source and drain regions

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs on a substrate. The MOSFETs include elevated source and drain regions. The elevated source and drain regions are adjacent ultra-shallow source and drain regions. Dopants in the ultra-shallow source and drain regions are activated in a low-temperature rapid thermal anneal process.

A new two-dimensional model for the potential distribution of short gate-length MESFET's and its applications

Abstract: A new analytical technique for calculating the 2-D potential distribution of a MESFET device operated in the subthreshold region is proposed, in which the 2-D Poisson's equation is solved by the Green's function technique. The potential and electric-field distributions of a non-self-aligned MESFET device are calculated exactly from different types of Green's function in different boundary regions, and the sidewall potential at the interface between these regions can be determined by the continuation of the electric field at the sidewall boundary. The remarkable feature of the proposed method is that the implanted doping profile in the active channel can be treated. Furthermore, a simplified technique is developed to derive a set of quasi-analytical models for the sidewall potential at both sides of the gate edge, the threshold voltage of short gate-length devices, and the drain-induced barrier lowering. Moreover, the developed quasi-analytical models are compared with the results of 2-D numerical analysis and good agreements are obtained. >

High voltage, high frequency double diffused metal oxide semiconductor device

Abstract: High voltage, high frequency metal oxide semiconductor device having a precisely controlled channel extending to the surface and in which a metallization overlies a thick insulating layer and substantially covers the depletion region in the drain for breakdown voltage control.