Topic
Drain-induced barrier lowering
About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.
Papers published on a yearly basis
Papers
More filters
TL;DR: In this paper, an analytical model of the threshold voltage for long channel double-gate metal-oxide-semiconductor field effect transistor is developed, applicable to both symmetric and asymmetric structures with thin films.
Abstract: An analytical model of the threshold voltage for long channel double-gate metal-oxide-semiconductor field effect transistor is developed, applicable to both symmetric and asymmetric structures with thin films ( 10). The model takes into account short-channel effects, carrier quantization and fringing-field induced barrier lowering induced by the high-permittivity gate layer. The model assumes a parabolic dependence of the potential with position in the silicon film at threshold, enabling the development of an analytical expression for the surface potential. Compared to previous models only derived for undoped films, the present approach considers both mobile charge and depleted charge terms in Poisson’s equation. The model is fully validated by numerical simulation and is used to predict the impact of the fringing-induced barrier lowering on the threshold voltage of double-gate devices as a function of the gate stack composition and the device gate length.
37 citations
Patent•
22 Jul 2002
TL;DR: In this paper, a semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film is presented.
Abstract: A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability. While in a standby status, a voltage equal to source voltage Vdd is applied to the gate of transistor MP0, a voltage lower than the source voltage is applied to the source, and bulk bias voltage VB equal to or higher than source voltage Vdd is applied to the channel region in order to minimize the drain current of transistor MP0, so that current path of logic circuit 10 is cut off, and the occurrence of leakage current is suppressed.
37 citations
TL;DR: In this article, a model for the drain I-V characteristics is proposed and a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the collection currents and the drain current in this region of operation.
Abstract: When a short-channel MOSFET is driven into the avalanche-induced breakdown region, the drain current increases rapidly and usually shows a snapback characteristic. Both the substrate current and the current collected by a nearby reverse-biased p-n junction also increases with increasing drain current in this region of operation. All of these effects are associated with minority-carrier injection from the source junction into the substrate. A model for the drain I-V characteristics is proposed. Also presented is a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the collection currents and the drain current in this region of operation. Experimental results agree well with the models.
37 citations
Patent•
TSMC1
TL;DR: In this paper, a strained channel transistor and a method for forming the strain channel transistor including a semiconductor rate, gate dielectric overlying a channel region, a gate rode overlying the gate dieslectric, source drain extension regions and source and drain (S/D) regions are presented.
Abstract: A strained channel transistor and method for forming the the strained channel transistor including a semiconductor rate; a gate dielectric overlying a channel region; a gate rode overlying the gate dielectric; source drain extension regions and source and drain (S/D) regions; wherein a sed dielectric portion selected from the group consisting of r of stressed offset spacers disposed adjacent the gate rode and a stressed dielectric layer disposed over the gate rode including the S/D regions is disposed to exert a strain channel region.
37 citations
TL;DR: In this paper, the performance of thin-film transistors with a poly-Si nanowire channel prepared by solid-phase crystallization is investigated and the major conduction mechanism of the off-state leakage is identified as the gate-induced drain leakage, and it is closely related to the source/drain implant condition and the unique device structure.
Abstract: The performance of thin-film transistors with a novel poly-Si nanowire channel prepared by solid-phase crystallization is investigated in this paper. As compared with conventional planar devices having self-aligned source/drain, the new devices show an improved on-current per unit width and better control over the short channel effects. The major conduction mechanism of the off-state leakage is identified as the gate-induced drain leakage, and it is closely related to the source/drain implant condition and the unique device structure
37 citations