Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Lateral high voltage transistor having spiral field plate and graded concentration doping

Abstract: A lateral high voltage transistor device is disclosed. The transistor includes a gate, a drain, and a source. The drain is located apart from the gate to form an intermediate drift region. The drift region has variable dopant concentration between the drain and the gate. In addition, a spiral resistor is placed over the drift region and is connected to the drain and either the gate or the source of the transistor.

Shielded channel double-gate MOSFET: a novel device for reliable nanoscale CMOS applications

Abstract: In this paper, the unique features exhibited by a novel double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) in which the front gate consists of two side gates to 1) electrically shield the channel region from any drain voltage variation and 2) act as an extremely shallow virtual extension to the source/drain are presented. This structure exhibits significantly reduced short-channel effects (SCEs) when compared with the conventional DG MOSFET. Using two-dimensional (2-D) and two-carrier device simulation, the improvement in device performance focusing on threshold voltage dependence on channel length, electric field in the channel, subthreshold swing, and hot carrier effects, all of which can affect the reliability of complementary metal oxide semiconductor (CMOS) devices, was investigated.

Power semiconductor structure with lateral transistor driven by vertical transistor

Abstract: A power semiconductor structure (200), in particular in VIPower technology, made from a chip of N-type semiconductor material (110), comprising a bipolar or field-effect vertical power transistor (125, 120, 110) having a collector or drain region in such N-type material (110); the semiconductor structure comprises a PNP bipolar lateral power transistor (210, 110, 220) having a base region in such N-type material (110) substantially in common with the collector or drain region of the vertical power transistor.

Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping

Abstract: Graded doping profile in the channel of vertical sub-100-nm nMOSFETs was investigated in this study. Conventional single-step ion implantation was used to form the asymmetric graded doping profile in the channel. No large-angle-tilt implant is needed. The device processing is compatible with conventional CMOS technology. In a graded-channel-doping device, with the higher doping near the source, drain induced barrier lowering (DIBL) and the off-state leakage current are reduced significantly. The graded doped channel also has a lower longitudinal electric field near the drain. Therefore, hot-carrier related reliability is improved substantially with this type of device structure.

A 60 nm channel length ferroelectric-gate field-effect transistor capable of fast switching and multilevel programming

Abstract: We demonstrate a 60 nm channel length ferroelectric-gate field-effect transistor (FeFET) with thin-film transistor structure and good electrical properties. The FeFET contains three oxide thin-films: SrRuO3 (bottom gate electrode), Pb(Zr,Ti)O3 (ferroelectric), ZnO (semiconductor). The FeFET drain current-bottom gate voltage (IDS−VGS) characteristics show a high ON/OFF ratio of 105. The drain current ON/OFF ratio was about three orders of magnitude for write pulse widths as narrow as 10 ns. Although the channel length is set at 60 nm, the conductance can be changed continuously by varying the write pulse width. Good retention properties for three-level data were demonstrated.