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Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.


Papers
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Journal ArticleDOI
TL;DR: In this article, an analytical sub-threshold surface potential model for short-channel MOSFETs is presented, where the effect of varying depth of the channel depletion layer on the surface potential has been considered.
Abstract: An analytical subthreshold surface potential model for short-channel MOSFET is presented. In this model, the effect of varying depth of the channel depletion layer on the surface potential has been considered. The effect of the depletion layers around the source and drain junctions on the surface potential, which is very important for short channel devices is included in this model. With this, the drawback of the existing models that assume a constant channel depletion layer thickness is removed resulting in a more accurate prediction of the surface potential. A pseudo-two-dimensional method is adopted to retain the accuracy of two-dimensional analysis yet resulting in a simpler manageable one-dimensional analytical expression. The subthreshold drain current is also evaluated utilizing this surface potential model.

34 citations

Journal ArticleDOI
Abstract: The creation of a semi insulating (SI) buffer layer in AlGaN/GaN High Electron Mobility Transistor (HEMT) devices is crucial for preventing a current path beneath the two-dimensional electron gas (2DEG). In this investigation, we evaluate the use of a gaseous carbon gas precursor, propane, for creating a SI GaN buffer layer in a HEMT structure. The carbon doped profile, using propane gas, is a two stepped profile with a high carbon doping (1.5 x 10(18) cm(-3)) epitaxial layer closest to the substrate and a lower doped layer (3 x 10(16) cm(-3)) closest to the 2DEG channel. Secondary Ion Mass Spectrometry measurement shows a uniform incorporation versus depth, and no memory effect from carbon doping can be seen. The high carbon doping (1.5 x 10(18) cm(-3)) does not influence the surface morphology, and a roughness root-mean-square value of 0.43 nm is obtained from Atomic Force Microscopy. High resolution X-ray diffraction measurements show very sharp peaks and no structural degradation can be seen related to the heavy carbon doped layer. HEMTs are fabricated and show an extremely low drain induced barrier lowering value of 0.1 mV/V, demonstrating an excellent buffer isolation. The carbon doped GaN buffer layer using propane gas is compared to samples using carbon from the trimethylgallium molecule, showing equally low leakage currents, demonstrating the capability of growing highly resistive buffer layers using a gaseous carbon source.

34 citations

Patent
19 Sep 1996
TL;DR: In this article, the authors show that, at the boundary between the source region and the channel forming region, portions where electric field concentrations occur are displaced from the portion where a channel is formed.
Abstract: In a process for manufacturing a thin film transistor having a semiconductor layer constituting source and drain regions and a channel forming region, by the semiconductor layer being made thinner in the source and drain regions than in the channel forming region a structure is realized wherein, at the boundary between the source region and the channel forming region and the boundary between the drain region and the channel forming region, portions where electric field concentrations occur are displaced from the portion where a channel is formed. By reducing the OFF current (the leak current) without also reducing the ON current, a high mutual conductance is realized.

34 citations

Patent
25 Oct 1993
TL;DR: In this article, a gate region is formed on a surface of the substrate and a drain region of the first conductivity type is formed in contact with a second end of the extended drain region.
Abstract: In a method for constructing a semiconducting device, within a substrate of a first conductivity type there is formed a well of second conductivity type. Within the well, an extended drain region of a first conductivity type is formed. An insulating region over the extended drain region is formed. A gate region is formed on a surface of the substrate. A first side of the gate region is adjacent to a first end of the extended drain region. A drain region of the first conductivity type is formed. The drain region is in contact with a second end of the extended drain region. A source region is formed on a second side of the gate region.

34 citations

Patent
Wen-Tai Wang1, Chung-Hui Chen1
30 Sep 2002
TL;DR: In this article, a new level-shifting circuit consisting of a first cascaded switch comprising a first NMOS transistor and a first zero threshold NMOS transistors is achieved.
Abstract: A new level-shifting circuit is achieved comprising: a first cascaded switch comprising a first NMOS transistor and a first zero threshold NMOS transistor, the second cascaded switch comprises a second NMOS transistor and a second zero threshold NMOS transistor, and the cross-coupled pull-up comprises a first PMOS transistor and a second PMOS transistor. The sources of both of these PMOS transistors are coupled to a high voltage supply. The gate of the second PMOS transistor and the drain of the first PMOS transistor are coupled to the drain of the first zero threshold NMOS transistor to form an inverted output. The gate of the first PMOS transistor and the drain of the second PMOS transistor are coupled to the drain of the second zero threshold NMOS transistor to form a non-inverted output.

34 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202330
202279
202161
202055
201958
201845