Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Subthreshold drain leakage currents in MOS field-effect transistors

Abstract: There are two contributions to the drain-source leakage current in MOS field-effect transistors for gate voltages below the extrapolated threshold voltage (V tx ) : 1) reverse-bias drain junction leakage current, and 2) a surface channel current that flows when the surface is weakly inverted. Nearly six orders of magnitude of drain-source current from the background limit imposed by the drain junction leakage to the lower limits of detection of most curve tracers (0.05 µA) are controlled by gate-source voltages below the extrapolated threshold voltage. It is shown that this current flows only for gate voltages above the intrinsic voltage V i , the gate voltage at which the silicon surface becomes intrinsic. For gate voltages between V i and V tx the surface is weakly inverted with the resulting channel conductivity being responsible for the drain-source current "tails" observed for gate voltages below V tx . The importance of the intrinsic voltage in designing low-leakage CMOS and standard PMOS circuitry is discussed.

High-voltage transistor

Abstract: In an active matrix electroluminescent display, a pixel containing a grounded conductive electric field shield between an EL cell and the switching electronics for the EL cell. In a method of fabricating the pixel, first, an EL cell switching circuit is formed, then an insulating layer is formed over the switching circuit and a conductive layer (the field shield) is formed over the insulating layer. A through hole is provided in the field shield such that an electrical connection can be made between the switching circuit and an EL cell. The EL cell is then conventionally formed on top of the shield layer. Consequently, the shield isolates the switching circuit from the EL cell and ensures that any electric fields produced in the EL cell do not interfere with the operation of the switching electronics. Furthermore, the switching circuitry for each cell contains two transistors; a low voltage MOS transistor and a high voltage MOS transistor. The low voltage transistor is controlled by signals on a data and a select line. When activated, the low voltage transistor activates the high voltage transistor by charging the gate of the high voltage transistor. This gate charge is stored between the gate electrode of the high voltage transistor and the electric field shield. Additionally, to improve the breakdown voltage of the high voltage transistor, a capacitive divider network is fabricated proximate the drift region of that transistor. As such, the network uniformly distributes an electric field over the drift region.

Forming a MOS transistor with a recessed channel

Abstract: A MOS transistor is fabricated by forming an inverse gate mask consisting of a lower silicon dioxide layer and an upper silicon nitride layer. The exposed channel region is thermally oxidized. The mask is removed to permit a source/drain implant. The oxide growth is removed so that the channel region is recessed. A differential oxide growth then serves to mask the source and the drain for channel threshold adjust and punch-through implants. A doped polysilicon gate is formed, with the thinner area of the differential oxide serving as the gate oxide. In the resulting structure, the punch-through dopant is spaced from the source and the drain, reducing parasitic capacitance and improving transistor switching speeds.

Body-tied triple-gate NMOSFET fabrication using bulk Si wafer

Abstract: We fabricated firstly body-tied triple-gate NMOSFETs that have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 116 nm. Fabrication process steps of the devices are compatible with that of conventional bulk planar channel MOSFET technology and explained in detail in this paper. This MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower I SUB / I D than planar channel DRAM cell transistors. By optimizing process further, it is expected that cost effective body-tied triple-gate MOSFETs can be applied to real Integrated Circuits (ICs).

Write once read only memory with large work function floating gates

Abstract: Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate transistor has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a large work function floating gate separated from the channel region by a gate insulator, and a control gate is separated from the floating gate by a gate dielectric. A plug is coupled to the first source/drain region and couples the first source/drain region to an array plate. A transmission line is coupled to the second source/drain region. The floating gate transistor can be programmed in two directions to trap charge in the high work function floating gate.