Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Field effect transistor with buried gate pattern

Abstract: A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.

Stacked channel heterojunction fet

Abstract: A field effect transistor comprising a high electron mobility field effect transistor (HEMT) portion and a metal-Schottky-gate field effect transistor (MESFET) portion having respective channel layers (10, 22) controlled by a common gate (26). At microwave and higher radio frequencies, the drain current capability of the HEMT portion reaches an upper limit; the MESFET portion takes over to provide drain current capability greater than this limit.

Asymmetric field effect transistor structure and method

Abstract: Disclosed are embodiments of an asymmetric field effect transistor structure (200a-c) and a method of forming the structure in which both series resistance in the source region (204, 304) (Rs) and gate (210, 310) to drain ((205, 305) capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay) Specifically, different heights (214, 215) of the source (204) and drain regions (205) and/or different distances (351, 352) between the source (304) and drain regions (305) and the gate (210, 310) are tailored to minimize series resistance in the source region (204, 305) (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate (210, 310) to drain (205, 305) capacitance (i.e., in order to simultaneously ensure that gate ( 210, 310) to drain (205, 305) capacitance is less than a predetermined capacitance value).

Contoured-tub fermi-threshold field effect transistor and method of forming same

Abstract: A Fermi-threshold field effect transistor includes a contoured-tub region of the same conductivity type as the source, drain and channel regions and having nonuniform tub depth. The contoured-tub is preferably deeper under the source and/or drain regions than under the channel region. Thus, the tub-substrate junction is deeper under the source and/or drain regions than under the channel region. The diffusion capacitance is thereby reduced compared to a tub having a uniform tub depth, so that a high saturation current is produced at low voltages. The contoured-tub may be formed by an additional implant into the substrate using the gate as a mask.

Transistors, methods of manufacturing a transistor and electronic devices including a transistor

Abstract: Transistors, methods of manufacturing a transistor, and electronic devices including a transistor are provided, the transistor includes a channel layer, a source and a drain respectively contacting opposing ends of the channel layer, a gate corresponding to the channel layer, a gate insulating layer between the channel layer and the gate, and a first passivation layer and a second passivation layer sequentially disposed on the gate insulating layer. The first passivation layer covers the source, the drain, the gate, the gate insulating layer and the channel layer. The second passivation layer includes fluorine (F).