Topic
Drain-induced barrier lowering
About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.
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Patent•
15 Jan 1999TL;DR: In this paper, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the vDMS transistor, and its drain region connected to p-type junction isolation region.
Abstract: The n-channel VDMOS transistor is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the VDMOS transistor, and its drain region connected to the p-type junction-isolation region. The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.
32 citations
Patent•
25 Jun 2002TL;DR: In this article, the authors proposed a field effect transistor (FE transistor) which has the advantage that a significant increase in the effective channel width for the current flow ION can be guaranteed relative to conventional transistor structures used up to the present.
Abstract: The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow ION can be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current IOFF. The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.
32 citations
TL;DR: In this paper, an analytical threshold voltage model for the dielectric pocket double gate (DP-DG) junctionless FETs (JLFETs) was proposed, where the channel potential function was obtained by solving 2D Poisson's equation using an evanescent mode analysis with suitable boundary conditions.
Abstract: This paper proposes an analytical threshold voltage model for the dielectric pocket double gate (DP-DG) junctionless FETs (JLFETs). The channel potential function has been obtained by solving 2-D Poisson’s equation using an evanescent mode analysis with suitable boundary conditions. The potential function has then been used for modeling the threshold voltage to investigate the effects of the DP thickness and length on the short-channel effects of the structure. The effects of source and drain depletion regions have been included for improving the accuracy of the model. The model results of DP-DG JLFETs have been compared with the simulation data obtained from the 2-D TCAD ATLAS device simulator.
32 citations
Patent•
19 Sep 1979
TL;DR: In this article, a complementary type MOS transistor device was proposed, which has source, drain and gate regions formed in the n-well region of a p-type semiconductor layer.
Abstract: A complementary type MOS transistor device is disclosed including a p-channel type MOS transistor having source, drain and gate regions formed in the n-well region which is formed in the surface area of a p-type semiconductor layer and an n-channel MOS transistor having source, drain and gate regions formed in said semiconductor layer. The semiconductor layer is formed on an n-type semiconductor body and a reverse bias voltage is applied between the semiconductor layer and the semiconductor substrate.
32 citations
Patent•
27 Jan 1994
TL;DR: In this article, a field effect transistor has been used for the detection of chemical species or photons using an external energy source for polarizing the drain, source and gate of the transistor, and a film which is conductive or which can be rendered conductive and which is sensitive to the chemical species to be detected.
Abstract: The invention relates to a detector or sensor for the detection of chemical species or photons. This detector uses a field effect transistor having a semiconducting material substrate (1) in which are defined a source (3) and a drain (5), a gate (9) separated from the substrate by an insulating layer, an external energy source for polarizing the drain, source and gate of the transistor, a film (11), which is conductive or which can be rendered conductive and which is sensitive to the chemical species or photons to be detected, and an ammeter for measuring an electric current variation of the transistor. The arrangement of the film (11) between the connections of the gate (9) and the drain (5) makes it possible to modify the polarization voltage of the transistor gate under the effect of the species to be detected, which is represented by a variation of the current between the drain and the source, when the transistor is correctly polarized.
32 citations