scispace - formally typeset
Search or ask a question
Topic

Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.


Papers
More filters
Journal ArticleDOI
TL;DR: In this paper, a model for CAD analysis of small geometry MOSFET's is presented, which includes drain induced barrier lowering phenomena, the narrow channel effect and the hot carrier phenomena.
Abstract: A d.c. model for the CAD analysis of small geometry MOSFET's is presented. It includes the drain induced barrier lowering phenomena, the narrow channel effect and the hot carrier phenomena. A single current expression valid in continuous way over the entire range of operation, including the subthreshold and the saturation regimes, is provided.

32 citations

Patent
Timothy S. Beatty1
23 Dec 1997
TL;DR: In this article, a method and apparatus for preventing charge damage to a protected structure during processing of a semiconductor device was proposed, where a first source/drain region of a protection transistor was coupled to a gate and a second source/drain region of the protection transistor is coupled to ground.
Abstract: A method and apparatus for preventing charge damage to a protected structure during processing of a semiconductor device. A first source/drain region of a protection transistor is coupled to a protected transistor gate. A second source/drain region of the protection transistor is coupled to ground. The protection transistor is then turned on during the processing of the device to ground the protected transistor gate.

32 citations

Journal ArticleDOI
TL;DR: In this article, the influence of drain bias on the threshold voltage instability in pentacene-based organic thin-film transistors (OTFTs) was studied, by applying different drain biases to adjust the channel carrier concentration in linear mode.
Abstract: In this letter, the influence of drain bias on the threshold voltage instability in pentacene-based organic thin-film transistors (OTFTs) was studied. By applying different drain biases to adjust the channel carrier concentration in linear mode, the threshold voltage shift was found to be proportional to the carrier concentration. The experimental data can be well quantitatively explained by the drain bias-stress theory developed for a-Si TFTs. The outcome gives the insight of the degradation mechanism of OTFTs and is important for the design of OTFT pixel circuit, OTFT analog amplifiers, or OTFT active loads.

32 citations

Journal ArticleDOI
TL;DR: In this article, a two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described.
Abstract: A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage VPT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, VBD, however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that VPT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. VBD, however, decreases as the channel length, oxide thickness and diffusion depth decrease. Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.

32 citations

Journal ArticleDOI
TL;DR: The thermal generation component of polycrystalline silicon TFTs off-current is analyzed experimentally and theoretically in this article, where hot hole injection, obtained by stressing the device at negative gate voltage and high source-drain voltage, has been used to reduce the electric field at the drain junction.
Abstract: The thermal generation component of polycrystalline silicon TFTs off-current is analysed experimentally and theoretically. In order to minimize the field-enhanced component of the leakage current, hot-hole injection, obtained by stressing the device at negative gate voltage and high source-drain voltage, has been used to reduce the electric field at the drain junction. After stress, the electrical characteristics in the off-regime are channel length independent and do not depend on gate voltage. This behaviour has been associated with the thermal generation-recombination processes occurring at the drain junction. Two-dimensional numerical simulations have been carried out with the program HFIELD, which has been modified to take into account the presence of gap states in polysilicon, and to incorporate the thermal generation-recombination processes by using the Shockley-Read-Hall statistics. Numerical simulations confirm that the generation occurs in the depletion region of the drain junction. The experimental I d - V ds characteristics measured at negative gate voltage have been compared with the calculated characteristics. The best fit with the experimental data was obtained only by using a rather short carrier lifetime (10 −12 s). The simulations indicate that a decrease of the density of states produces a lower off-current owing to a longer carrier lifetime and to a reduction of the drain junction depletion layer.

32 citations


Network Information
Related Topics (5)
Transistor
138K papers, 1.4M citations
93% related
Silicon
196K papers, 3M citations
84% related
Capacitor
166.6K papers, 1.4M citations
83% related
Thin film
275.5K papers, 4.5M citations
82% related
Voltage
296.3K papers, 1.7M citations
81% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202330
202279
202161
202055
201958
201845