Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Three-dimensional analytical subthreshold models for bulk MOSFETs

Abstract: Three-dimensional device-physics-based analytical models are developed for subthreshold conduction in uniformly doped small geometry (i.e., simultaneously short channel and narrow width) bulk MOSFETs, for various isolation schemes. Inverse-narrow width effects, where the threshold voltage decreases with decreasing channel width, are predicted by the model for trench isolated MOSFETs. For LOGOS isolated MOSFETs, conventional narrow width effects, where the threshold voltage increases due to decreasing channel width, are predicted. The narrow width effects are found to be comparable to the short channel effects in the absence of significant applied drain biases. However, for larger drain biases, the short channel effects outweigh the narrow width effects due to the weaker potential perturbation at the device width edges compared to the drain end. Unlike the threshold voltage, the subthreshold swing of the device is found to increase with reduced device dimensions regardless of the isolation scheme since both conventional and inverse narrow width effects result in weaker control of the surface potential by the gate.

The “barrier mode” behaviour of a junction FET at low drain currents

Abstract: The behaviour of a junction FET with a gate-source reverse bias exceeding the pinch-off voltage is discussed. It is seen that both the transfer and output characteristics have an exponential character, and this is attributed to the presence of a potential barrier between the source and drain. Simple expressions are given for both the conductance and transconductance in terms of parameters which, in the case of long gate devices, may be evaluated analytically, or, in the case of short gate devices, evaluated numerically using a relatively simple computer model.

Fast dynamic low-voltage current mirror with compensated error

Abstract: A current mirror comprising: a current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel transistor, and a drain; a first n-channel MOS transistor having a source coupled to ground, and a gate and a drain coupled to the drain of the second p-channel transistor; a zero-threshold n-channel MOS transistor having a drain coupled to a current-output node, a gate coupled to the gate of the first n-channel transistor, and a source; and a second n-channel MOS transistor having a source coupled to ground, and a gate coupled to the gate of the first n-channel transistor and a drain coupled to the source of the zero-threshold n-channel transistor.

Quantum Simulation Study of a New Carbon Nanotube Field-Effect Transistor With Electrically Induced Source/Drain Extension

Abstract: In this paper, we present the unique features exhibited by a proposed structure of coaxially gated carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions using the self-consistent and atomistic scale simulations, within the nonequilibrium Green's function formalism. In this novel CNTFET structure, three adjacent metal cylindrical gates are used, where two side metal gates with lower workfunction than the main gate as an extension of the source/drain on either side of the main metal gate are biased, independent of the main gate, to create virtual extensions to the source and the drain and also to provide an effective electrical screen for the channel region from the drain voltage variations. We demonstrate that the proposed structure of CNTFET shows improvement in device performance focusing on leakage current, on-off current ratio, and voltage gain. In addition, the investigation of short-channel effects for the proposed structure shows improved drain-induced barrier lowering, hot-carrier effect, and subthreshold swing, all of which can affect the reliability of CMOS devices.

Short-channel field effect transistor

Abstract: An improved short-channel field effect transistor including a standard tip implant type of source and drain each disposed in the surface of a semiconductor substrate and a gate electrode positioned upon the substrate between the source and drain and control plugs disposed in the substrate and associated with and contiguous to the source and drain for eliminating substrate punch-through currents without substantially increasing the device junction capacitance.