Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Programmable memory cell using charge trapping in a gate oxide

Abstract: An illustrative embodiment of the present invention includes a non-volatile, reprogrammable circuit switch. The circuit switch includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide. According to the teachings of the present invention, the MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).

New ratio method for effective channel length and threshold voltage extraction in MOS transistors

Abstract: A new 'ratio' method for effective channel length and threshold voltage extraction in MOS transistors is proposed. The method, which relies on the same function as that used in the well known shift and ratio procedure, enables the effective channel length and threshold voltage difference to be extracted from simple linear regression applied to a short versus long channel correlation plot of the function Y(V/sub g/)=I/sub d//spl radic/g/sub m/ (I/sub d/ being the drain current and g/sub m/ the transconductance). This method has successfully been applied to 0.18-0.1 /spl mu/m CMOS technologies.

Design considerations for 25 nm MOSFET devices

Abstract: This paper presents the results of a systematic theoretical investigation on scaling gate oxide thickness and the source-drain extension (SDE) junction depth to design high performance MOSFET devices with effective channel lengths near 25 nm. In order to obtain 25 nm MOSFETs, CMOS technologies with 40, 50, and 60 nm gate lengths were designed by scaling SDE junction depth to 14, 20, and 26 nm, respectively. Each technology with the target gate oxide thickness was optimized for an off-state leakage current ∼10 nA/μm for 25 nm devices and the device characteristics were obtained for an equivalent gate oxide thickness of 1, 1.5, and 2 nm. The results show that for a target off-state leakage current of 25 nm devices the magnitude of threshold voltage, sub-threshold slope, and drain-induced barrier lowering increases while the magnitude of drive current decreases with the increase of gate oxide thickness. On the other hand, the variation in the magnitude of threshold voltage, sub-threshold slope, drain-induced barrier lowering, and the drive current for the similar devices is insignificant within the range of SDE junction depth 14–26 nm. It is, also, found that the gate delay for 25 nm devices increases with the increase of SDE junction depth. This study, clearly, demonstrates the importance of scaling gate oxide thickness and the SDE junction depth below the presently reported limits to design high performance 25 nm MOSFET devices for low voltage application.

Effects of oxide interface traps and transient enhanced diffusion on the process modeling of PMOS devices

Abstract: We present a model which simulates the trapping of arsenic and boron dopants at the silicon-silicon dioxide interface, and demonstrate that this model gives significantly more accurate doping profiles for a wide range of PMOS devices, as characterized by the device Threshold Voltage. In addition, a newly-developed Transient Enhanced Diffusion (TED) model is applied for the first time to the process simulation of buried-channel PMOS devices, predicting an enhanced Short Channel Effect and Drain Induced Barrier Lowering (DIBL) effect. By using both these models, an excellent agreement is achieved between simulated and measured device characteristics for PMOS devices with gate lengths varying from 2 to 0.4 /spl mu/m, over a wide range of bias conditions and operating temperatures.

Fermi threshold field effect transistor including doping gradient regions

Abstract: A high saturation current, low leakage, Fermi threshold field effect transistor includes a predetermined minimum doping concentration of the source and drain facing the channel to maximize the saturation current of the transistor Source and drain doping gradient regions between the source/drain and the channel, respectively, of thickness greater than 300Å are also provided The threshold voltage of the Fermi-FET may also be lowered from twice the Fermi potential of the substrate, while still maintaining zero static electric field in the channel perpendicular to the substrate, by increasing the doping concentration of the channel from that which produces a threshold voltage of twice the Fermi potential By maintaining a predetermined channel depth, preferably about 600Å, the saturation current and threshold voltage may be independently varied by increasing the source/drain doping concentration facing the channel and by increasing the excess carrier concentration in the channel, respectively A Fermi-FET having a gate insulator thickness of less than 120Å, and a channel length of less than about 1 μm can thereby provide a P-channel saturation current of at least 4 amperes per centimeter of channel width and an N-channel saturation current of at least 7 amperes per centimeter of channel width, with a leakage current of less than 10 picoamperes per micron of channel length using power supplies of between 0 and 5 volts