Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Threshold voltage in short-channel MOS devices

Abstract: The threshold voltage in short-channel MOS transistors was investigated by use of a two-dimensional numerical solution of Poisson's equation and experimental measurements on devices of 5.15-, 3.15-, and 2.15-µm channel length. The assumption of constant equipotential surface in the oxide implicit in the charge-sharing technique is not valid in devices of shorter Channel lengths and at larger operating voltages. The numerical determination of the threshold voltage from the two-dimensional analysis agrees with experimental results. Unlike previous work, the charge-sharing model was investigated from an electric-field point of view. The inadequacies of the charge-sharing model are elucidated qualitatively and quantitatively.

Recovery of threshold voltage after hot-carrier stressing

Abstract: The recovery of threshold voltage due to high drain or gate voltage and the effects of hot-carrier stressing on the drain breakdown voltage of MOSFETs have been studied. A high oxide field causes slow recovery through tunneling detrapping of electrons in both p- and n-MOSFETs. For n-MOSFETs the mechanism of fast recovery is low-level hole injection at high V/sub D/. Hot-carrier stressing at high V/sub G/ causes the drain breakdown voltage to decrease (walk-in). This results in enhanced hold injection, thus increasing the rate of subsequent recovery of V/sub t/. The breakdown voltage increases and then decreases when stressed at low gate voltages. >

High voltage transistors with graded extension

Abstract: High voltage transistors with high breakdown voltages are provided. These high voltage transistors are formed with graded drain extension regions. The concentration of charge carriers increases farther away from the gate across each drain extension region, causing severe electric fields to be moved away from the gate. Methods and structures of the present invention may be used to increase a transistor's breakdown voltage to the theoretical limit of the device. High voltage transistors with graded extension regions may be p-channel or n-channel MOSFETs.

Kilowatt power transistor

Abstract: A high-power high-voltage transistor has four or more semiconductor dies (14) mounted in thermal contact on a metal flange (12). Each die (14) has a flat lower surface with a drain (collector) region formed over at least 80 percent of its lower surface. A gate (base) region and a source (emitter) region are formed respectively on upper surfaces of the did. The drain region is seated in direct electrical and thermal contact with the flange (12), so that the flange serves as a drain lead for the transistor did (14). The did has a drain-source breakdown voltage (or collector-emitter breakdown voltage) on the order of one kilovolt or higher and an area of one hundred thousand square mils or larger. Molybdenum tabs (57) between the drain (collector) region and the flange protect the did from thermally-induced stresses. The dies can be MOSFET power transistors, bipolar junction transistors or other solid-state devices. An oval lead frame (60) can be employed for connecting to the source regions. A carousel arrangement carries an array of chips (114) on a circular flange (112). The transistor can be implemented as a DC grounded drain, RF common source amplifier circuit. The gate-source input can float, allowing the drain to be DC and thermally grounded. The RF current path is conventional common source (emitter).

Two transistor flash EPROM cell

Abstract: A two-transistor flash EPROM cell includes a first floating gate transistor for programming the cell and a second merged transistor for reading the cell. The first transistor, a floating gate transistor, has a drain coupled to the write bit line, a gate coupled to the word line, and a source coupled to the source line. The merged transistor effectively consists of a floating gate transistor in series with a NMOS enhancement transistor. The series NMOS transistor has a voltage threshold of about 1 to 2 volts, thus preventing cell activation caused by overerasure (negative voltage threshold) of the floating gate transistor.