Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor

Abstract: The vertical transistor includes, on a semiconductor substrate, a vertical pillar 5 having one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar, a gate dielectric layer 7 situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The gate includes a semiconductor block having a first region 800 resting on the gate dielectric layer 7 and a second region 90 facing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavities 14 S, 14 D.

Method for reduction of reverse short channel effect in MOSFET

Abstract: This invention describes a manufacturing method for MOSFET devices that are free from reverse short channel effect usually found in such devices made by prior art processes. In contrast to the prior art process sequence, the channel implant is made after the source and drain already formed by implantation and its damage already annealed out. The enhanced diffusion of the channel implant, caused by damage generated point defects and responsible for the reverse short channel effect, is therefore avoided. The channel implantation uses high energy ions to penetrate through the polysilicon gate, forming a threshold voltage adjustment and punch-through barrier layer under the gate. The channel implant through the source/drain regions is deeper than the source/drain junctions so that the junction capacitance is reduced in comparison with the prior art.

Integrated circuit device with series-connected field effect transistors and integrated voltage equalization and method of forming the device

Abstract: Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body.

A novel graphene nanoribbon field effect transistor with two different gate insulators

Abstract: In this paper, a novel structure for a dual-gated graphene nanoribbon field-effect transistor (GNRFET) is offered, which combines the advantages of high and low dielectric constants. In the proposed Two Different Insulators GNRFET (TDI-GNRFET), the gate dielectric at the drain side is a material with low dielectric constant to form smaller capacitances, while in the source side, there is a material with high dielectric constant to improve On-current and reduce the leakage current. Simulations are performed based on self-consistent solutions of the Poisson equation coupled with Non-Equilibrium Green's Function (NEGF) formalism in the ballistic regime. We assume a tight-binding Hamiltonian in the mode space representation. The results demonstrate that TDI-GNRFET has lower Off-current, higher On-current and higher transconductance in comparison with conventional low- K GNRFET. Furthermore, using a top-of-the-barrier two-dimensional circuit model, some important circuit parameters are studied. It is found that TDI-GNRFET has smaller capacitances, lower intrinsic delay time and shorter power delay product (PDP) in comparison with high- K GNRFET. Moreover, mobile charge and average velocity are improved in comparison with low dielectric constant GNRFET. The results show that the TDI-GNRFET can provide Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing near their theoretical limits.

Semiconductor transmission gate with capacitance compensation

Abstract: A transmission gate employs a pair of capacitors ahead of and a pair of capacitors behind a transistor. One capacitor of each pair is supplied with a control voltage pulse that leads and the other with a control voltage pulse that lags the complement of a control voltage pulse supplied to the gate of the transistor. The capacitors are typically each a MOS transistor with the gate serving as one terminal and the drain and source shorted together and serving as the other terminal. Moreover, each of the capacitors has a capacitance equal to one half the capacitance of the gate to source and gate to drain capacitance of the transistor. This circuitry makes possible charge compensation to avoid the build up of trapped charge in the transistor. The capacitance of the pair of capacitors ahead of the transistor is approximately equal to the gate-to-drain parasitic of the transistor and the capacitance of the pair of capacitors behind the transistor is equal to the parasitic capacitance of the gate-to-source of the transistor.