Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Thin-film transistor with fully gated channel region

Abstract: A semiconductor device (10) has a thin-film transistor (TFT) formed in and around an opening (24) in a dielectric layer (22). A conductive layer (26) lines the opening sidewalls and serves as a gate electrode of the transistor. A conductive layer (30) is deposited over the gate electrode to form a source region (32), a channel region (36), and a drain region (34). The two conductive layers are separated by a gate dielectric (28). Because both the gate electrode and the channel region conform to the opening sidewalls and bottom, the entire channel region is under direct gate control. Device (10) may also include a conductive region, such as a gate electrode (15) of a bulk transistor, at the bottom of opening (24) and in electrical contact with the TFT gate electrode.

CMOS 3.3 volt output buffer with 5 volt protection

Abstract: As VLSI chip design migrates from 5 volt designs to lower voltage designs, such as 3.3 volts, interfacing components with different power supplies is an unavoidable issue. This invention provides simple and inexpensive circuits which will pass the voltage at the output node of a CMOS buffer circuit to the isolation well of the P channel metal oxide semiconductor field effect transistor in the buffer circuit when the voltage at the output node is greater than the voltage at the buffer voltage supply node. This prevents forward biasing the PN junction in the isolation well of the P channel metal oxide semiconductor field effect transistor. The circuits also provide the proper voltage level to the gate of the P channel field effect transistor.

A simple procedure to extract the threshold voltage of amorphous thin film MOSFETs in the saturation region

Abstract: A technique is presented to extract the threshold voltage of amorphous thin film MOSFETs in the saturation region. The technique is proposed because threshold voltage extraction in amorphous TFTs is different, and in general more complex, than in conventional crystalline bulk devices, since these TFTs exhibit several notable dissimilarities inherent to their characteristics. The saturation drain current follows an m power-law type dependence on gate bias, with an m different from the conventional value of 2. Additionally, a plot of the saturation current as a function of gate bias does not reveal the existence of an inflexion point. The method presented, which extracts the value of the power-law parameter m as well, is based on the use of an auxiliary operator that involves the integration of the drain current as a function of gate voltage. The technique was tested and its accuracy verified using the measured characteristics of an experimental n-channel a-Si:H thin film MOSFET.

Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length

Abstract: In this paper, for the first time, we have investigated the DC and analog/RF performance metrics of 3 nm gate length (LG) silicon-on-insulator (SOI) FinFET using HfxTi1−xO2 high-k material in gate stack to improve subthreshold characteristics. The 3-D device performance of single-k, dual-k, and hybrid spacer is compared without spacer dielectric, and DC characteristics are presented. In this move, it is noticed that the device attains the highest ION/IOFF ratio of ~109 compared to ~105 due to an increase of effective gate length by fringing fields with spacer dielectric. Moreover, to evaluate and understand the nanostructure performance comparison is made between Junctionless (JL), Accumulation (ACC), and Inversion (INV) modes. The device exhibits excellent DC characteristics with ION/IOFF ratio of ~109, subthreshold swing (SS) of ~61.8 mV/dec, drain induced barrier lowering of (DIBL