Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

On the temperature variation of threshold voltage of GaAs MESFETs

Abstract: The authors have investigated the temperature dependence of the threshold voltage of depletion-mode GaAs MESFETs with epitaxially grown n channels. An approach to threshold shift analysis that allows direct comparison with threshold measurement is taken. The contributions from various temperature-dependent effects to the threshold-voltage shift were studied, including the built-in voltage of the Schottky barrier, deep-level transients, capping layer effects, the substrate-channel built-in voltage, and the k factor which is related to channel mobility. A quasi-DC method for threshold voltage measurement, which enables threshold voltage to be measured as a function of temperature with minimum deep-level transient effect is reported. A method has also been developed to measure the temperature dependence of built-in voltage which is completely free from transient effects. The results show that the major contributors to the temperature variation of threshold voltage are the temperature dependence of the Schottky barrier built-in voltage and the effect of the capping layer. >

EEPROM memory cell and method of fabricating the same

Abstract: An object of the present invention is to realize a memory cell including a single polysilicon layer so as to simplify the fabrication process, improve the productivity and lower the fabrication cost of the memory cell. Another object of the present invention is to realize a memory cell with a simple structure as well as to reduce the area of the memory cell so as to attain high integration. Still another object of the present invention is to form a fine memory cell by utilizing DHE (drain channel hot electrons) and GIDL (gate induced drain leakage). An EEPROM memory cell 10 includes a substrate 12 ; a source region 14 and a drain region 16 formed on a surface of the substrate 12 ; a channel region 18 defined on the surface of the substrate 12 between the source region 14 and the drain region 16 ; a gate oxide film 20 formed on the channel region 18 so as to partly overlap with the source region 14 and the drain region 16 ; and a gate 22 including polysilicon formed on the gate oxide film 20.

Method and apparatus for a two phase bootstrap charge pump

Abstract: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage. A first series of clock pulses is applied to the gate terminals of the first switching transistor devices in every other stage of the charge pump and to the gate terminals of the second control transistor devices in stages between; and a second series of clock pulses which do not overlap the first series of clock pulses is applied to the gate terminals of the first switching transistor devices in alternate stages of the charge pump and to the gate terminals of the second control transistor devices in stages between the alternate stages. These pulses cause the switching transistor to switch on and off in alternate stages in a manner that the gate terminal goes higher than the drain terminal so that charge is transferred without threshold drop between stages and high current as well as high voltage is pumped to the output terminal.

Single poly non-volatile memory

Abstract: An erasable programmable non-volatile memory cell encompasses an ion well; a first select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; a first floating gate transistor having a drain, a source coupled to the drain of the first select transistor, a first floating gate channel region formed between its drain and source, and a common floating gate overlying the floating gate channel region; a second select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; and a second floating gate transistor having a drain, a source coupled to the drain of the second select transistor, a second floating gate channel region formed between its drain and source, and the common floating gate overlying the second floating gate channel region.

Field effect transistor with electrically induced drain and source extensions

Abstract: For fabricating a field effect transistor within an active device area of a semiconductor substrate, a gate dielectric is formed on the active device area of the semiconductor substrate, and a gate structure is formed on the gate dielectric with the gate structure being comprised of a first conductive material. A drain spacer comprised of a second conductive material is formed on a first sidewall of the gate structure, and a first liner dielectric is formed between the drain spacer and the first sidewall of the gate structure and between the drain spacer and the semiconductor substrate. A source spacer comprised of the second conductive material is formed on a second sidewall of the gate structure, and a second liner dielectric is formed between the source spacer and the second sidewall of the gate structure and between the source spacer and the semiconductor substrate. Application of at least a drain threshold voltage on the drain spacer with respect to the semiconductor substrate induces charge accumulation in the semiconductor substrate under the first liner dielectric to form a drain extension of the field effect transistor. Similarly, application of at least a source threshold voltage on the source spacer with respect to the semiconductor substrate induces charge accumulation in the semiconductor substrate under the second liner dielectric to form a source extension of the field effect transistor. In this manner, the drain and source extensions of the field effect transistor are electrically induced to have a depth that is shallow regardless of thermal processes used for fabrication of the integrated circuit having the field effect transistor.