scispace - formally typeset
Search or ask a question
Topic

Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.


Papers
More filters
Patent
Joseph C. Buxton1
14 Jun 2001
TL;DR: In this paper, a linear voltage regulator using a FET pass transistor uses the capacitance of the pass transistor's gate as a timing element, and when it droops below a voltage indicative of a short-circuit condition, the regulator's drive signal is disconnected from the FET's gate.
Abstract: A hiccup-mode short circuit protection circuit and method for a linear voltage regulator using a FET pass transistor uses the capacitance of the pass transistor's gate as a timing element. The regulator's output voltage is monitored, and when it droops below a voltage indicative of a short-circuit condition, the regulator's drive signal is disconnected from the pass transistor. While the short-circuit condition persists, a first current is provided to charge the pass transistor's gate capacitance. When the gate voltage rises above a first predetermined threshold, a second current is provided to further charge the gate capacitance. When the gate voltage rises above a second predetermined threshold, the gate capacitance is discharged. The gate capacitance is cyclically charged and discharged in this way unless the output voltage rises to indicate that the short-circuit condition has cleared, in which case the regulator's drive signal is restored to the pass transistor's gate. To reduce average power consumption, the magnitudes of the first and second currents and the values of the threshold voltages are chosen such that the pass transistor's ON duty cycle is about 10%.

29 citations

Patent
05 Mar 1991
TL;DR: In this paper, the authors present a method and structure for actively controlling the voltage applied to the channel of field effect transistors (FE transistors), where a transistor is fabricated to connect the channel region to the main channel region.
Abstract: The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabricated. The channel transistor has opposite conductivity type to the transistor using the main channel region. The source of the channel transistor is connected to the channel and the drain of the channel transistor is connected to a reference voltage. The same gate is used to control the channel transistor and the main transistor. When a voltage which causes the main transistor to be on is applied, the channel transistor is off, thus allowing the channel to float and allowing higher drive current. On the other hand, when a voltage to turn off the main transistor is applied, the channel transistor is turned on, thus clamping the channel region to the reference voltage. This allows for consistent threshold voltage control of the main transistor. In a preferred embodiment, the channel of the main transistor is used as the source of the channel transistor and the gate of the main transistor extends onto the channel region of the channel transistor. The reference voltage is then connected to the drain region which is formed on the opposite side of the channel transistor channel region from the main transistor's channel.

29 citations

Patent
Kaizad Mistry1, Ian R. Post1
18 Nov 1999
TL;DR: In this article, a method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least four active regions in a substrate, each region having different doping profile is presented.
Abstract: A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.

29 citations

Patent
27 Jul 2005
TL;DR: In this article, a method and apparatus is presented that provides mobility enhancement in the channel region of a transistor, where the source and drain regions provide an additional uni-axial stress to the bi-axially stressed channel region.
Abstract: A method and apparatus is presented that provides mobility enhancement in the channel region of a transistor. In one embodiment, a channel region (18) is formed over a substrate that is bi-axially stressed. Source (30) and drain (32) regions are formed over the substrate. The source and drain regions provide an additional uni-axial stress to the bi-axially stressed channel region. The uni-axial stress and the bi-axial stress are both compressive for P-channel transistors and both tensile for N-channel transistors. The result is that carrier mobility is enhanced for both short channel and long channel transistors. Both transistor types can be included on the same integrated circuit.

29 citations

Journal ArticleDOI
TL;DR: In this paper, a self-consistent OFET model has been developed for bottom-contact organic transistor, and is described in detail, where most relevant contact parasitics are taken into account, such as source and drain series resistances, leakage source/drain resistance, and of course nonlinear charge injection at the source contact, being the focus of this work.

29 citations


Network Information
Related Topics (5)
Transistor
138K papers, 1.4M citations
93% related
Silicon
196K papers, 3M citations
84% related
Capacitor
166.6K papers, 1.4M citations
83% related
Thin film
275.5K papers, 4.5M citations
82% related
Voltage
296.3K papers, 1.7M citations
81% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202330
202279
202161
202055
201958
201845