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Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.


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Proceedings ArticleDOI
06 Mar 2012
TL;DR: In this article, the authors derived an analytical two-dimensional model to calculate the potential within ultra-scaled junctionless double-gate MOSFETs valid in sub-threshold region.
Abstract: We derived an analytical two-dimensional model to calculate the potential within ultra-scaled junctionless double-gate MOSFETs (DG MOSFETs) valid in subthreshold region. We propose an approach how to calculate the threshold voltage of such devices, and present our first results. Compared to conventional MOSFETs, the proposed junctionless transistor has no pn-junctions. Its type of doping in the channel region is the same as in the source/drain. The device is turned on by creating a conducting channel in the center of the silicon, and turned off by depleting it. To ensure a safe switching behavior, the investigation of the subthreshold region is therefore important. A Comparison of our model with numerical simulation results confirms its validity for ultra-scaled devices having a channel length about 22 nm.

29 citations

Journal ArticleDOI
TL;DR: In this paper, the degradation of drain current and the properties of flicker noise in n-channel Lightly-Doped Drain (LDD) MOSFETs due to hot-electron injection were studied.
Abstract: We have studied the degradation of drain current and the properties of flicker noise in n-channel Lightly-Doped Drain (LDD) MOSFETs due to hot-electron injection. The two types of devices examined were shallow double-diffused drain and deep double-diffused drain MOSFETs. It was found that the flicker noise level is highly sensitive to hot-electron injection. The increase in flicker noise and drain current degradation in the shallow double-diffused drain devices were significantly more than the deep double-diffused drain devices, indicating improved hot-electron hardness in the latter. However, the pre-stressed flicker noise magnitudes in the deep double-diffused drain transistors were about two orders of magnitude higher than the shallow double-diffused drain transistors. This is possibly due to creation of defects during the high energy phosphorus implantation step in the fabrication of the deep drain junction.

29 citations

Journal ArticleDOI
TL;DR: In this article, position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel and peaked in Drain junction space charge layer.
Abstract: Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 /spl mu/m n-channel Si MOS transistor with about 10/sup 11/ traps/cm/sup 2/ generated by channel hot electron stress.

29 citations

Journal ArticleDOI
TL;DR: In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a nonplanar structure is experimentally studied in triple-gate FinFETs, and the drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) is analyzed in the DT mode and the standard biasing configuration.
Abstract: In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-planar structure is experimentally studied in triple-gate FinFETs. The drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DT mode and the standard biasing configuration. Moreover, for the first time, the important figures of merit for the analog performance such as transconductance-over-drain current, output conductance, Early voltage and intrinsic voltage gain will be studied experimentally and through three-dimensional (3-D) numerical simulations for different channel doping concentrations in triple-gate DTMOS FinFETs. The results indicate that the DTMOS FinFETs always yield superior characteristics and larger transistor efficiency. In addition, DTMOS devices with a high channel doping concentration exhibit much better analog performance compared to the normal operation mode, which is desirable for high performance low-power/low-voltage applications.

29 citations

Patent
25 Jul 1991
TL;DR: In this article, a nonvolatile memory cell with heavily doped source 12 and drain 14 regions separated by a channel region 16 is presented. And the cell is programmed by applying a nearly reference voltage V s to the source region 12 and a drain voltage V D to the drain region 14.
Abstract: A non-volatile memory cell includes heavily doped source 12 and drain 14 regions separated by a channel region 16. The source 12 and drain 14 are isolated from floating gate 18 and control gate 22 by thick oxide 36. A floating gate 18 is formed over and insulated from a portion of said channel region 16 adjacent to the source 12 and a control gate 22 is formed over and insulated from the floating gate 18 and the remaining portion of the channel region 16. The cell is programmed by applying a nearly reference voltage V s to the source region 12 and applying a drain voltage V D to the drain region 14. A gate voltage V G is applied to the control gate 22 such that an inversion region 15 is formed in the remaining portion of said channel region 16 such that the floating gate 18 is charged up by hot electron injection on the side away from the source junction. The source junction is self aligned to floating gate and is graded for efficient erase. Other key features and methods are also disclosed.

29 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202330
202279
202161
202055
201958
201845