Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Process variation study of Ground Plane SOI MOSFET

Abstract: In this paper, the variations of the main characteristics in three SOI device structures due to channel length and thin-film thickness variations are investigated. The structures are studied in a 32nm technology and include SOI-GPS (Ground-Plane in Substrate), SOI-GPB (Ground-Plane in BOX), and SOI-WGP (Without Ground Plane). For this study, we assume normal distributions for the channel length and thin-film thickness of the transistors and then obtain the distributions for the threshold voltage, leakage, DIBL coefficient, and subthreshold swing. The results show that the GPS structure is more resistant against the variations when compared to the other two structures.

An analytical two-dimensional simulation for the GaAs MESFET drain-induced barrier lowering: a short-channel effect

Abstract: An analytic model for simulating the GaAs MESFET drain-induced barrier lowering and its effect on device performance are discussed. The potential barrier between the source and drain of a field-effect transistor in or near the subthreshold region is lowered by increasing the drain voltage. As the barrier is lowered to be comparable to the thermal energy, an appreciable current will flow through the channel, and the device will begin to conduct. This effect causes the threshold-voltage-control problem and degrades the device performance. >

Power FET short circuit protection

Abstract: A protection circuit for a semiconductor device such as a field effect transistor is disclosed having an oscillator which is connected to both the gate turn on circuitry and to the drain-source circuit of the field effect transistor for sensing the voltage of the drain-source circuit and for turning off cyclically the field effect transistor upon the simultaneous occurrence of a gate turn on signal to the gate of the transistor and high drain-source voltage.

Insulated gate type bipolar transistor

Abstract: PURPOSE: To eliminate a latchup by controlling a first carrier electric resistance value by a source layer shape between a first contact and a channel region, and preventing conduction of a pn junction. CONSTITUTION: A p + type silicon substrate is prepared, and an n - type layer of low impurity concentration semiconductor is formed by an epitaxial growth. A p + type drain layer 1, an n - type drain layer 2 are formed of the substrate and the n - type layer, and the surface of the layer 2 is oxidized to form a gate oxide film 3. A gate electrode 4 of a polysilicon film is formed thereon. With the electrode 4 as a mask boron is diffused to form a p-type base layer 5. Then, the center of the window of the electrode 4 is covered with a resist film patterned in a shape opened in a T shape, phosphorus ions are implanted to form an n + type source layer 6. Since carrier electric resistance value R 1 is controlled by the shape of the layer 6 to prevent conduction of the pn junction, a source resistance is improved to prevent a latchup. COPYRIGHT: (C)1992,JPO&Japio

An analysis of current saturation mechanism of junction field-effect transistors

Abstract: A two-dimensional numerical analysis has been amde for junction field-effect transistors with small and large values of length-to-width ratio. Comparison of the results for different drain bias voltages shows the cause of the saturation of the drain current and the finite differential drain conductance in the saturation region. The effects of the geometry of the device and the field dependent mobility to the drain characteristics are clarified. Detailed pictures of the free carrier density distribution are presented, and the minimum channel width and the channel length are given for various bias conditions. A conduction path from the source to the drain with appreciable free carrier density has been found for bias conditions normally considered as pinched-off conditions. The drain characteristic with gate bias voltage is seen to be equivalent to that of a device with correspondingly smaller width and zero gate bias.