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Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.


Papers
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Journal ArticleDOI
M. Pinto-Guedes1, P.C. Chan1
TL;DR: The successful modeling of short-channel transistor breakdown characteristics with effective channel length down to 0.6 mu m is reported, the first successful application of a short- channel breakdown model in a circuit simulator.
Abstract: The successful modeling of short-channel transistor breakdown characteristics with effective channel length down to 0.6 mu m is reported. The sudden increase in the MOS drain current due to threshold voltage reduction caused by the forward biasing of the source-substrate junction is also modeled with considerable accuracy. This is the first successful application of a short-channel breakdown model in a circuit simulator. Model parameter extraction and installation of the model in the circuit simulator is also discussed. >

28 citations

Journal Article
TL;DR: The impact of channel engineering on double gate MOSFET is investigated by using different channel doping and it is observed in the results that the threshold voltage can be changed by changing the channel doping.
Abstract: Double gate MOSFET is one of the most promising and leading contender for nano regime devices. In this paper we investigate the impact of channel engineering on double gate MOSFET by using different channel doping. Sentaurus TCAD simulator is used to analyze the channel engineering of double gate MOSFET. It is observed in the results that we can change the threshold voltage by changing the channel doping. The impact of channel engineering also observed on performance parameters of the DG-MOSFET such as on current, off current, drain induced barrier lowering, subthreshold slope and carrier mobility. Thus, an optimized value of the channel doping will be projected for future reference in context of leakage power. Thus channel engineering will play an important role in optimizing the device parameters. General Terms Integrated Circuit, VLSI, MOS Device Modeling.

28 citations

Journal ArticleDOI
TL;DR: In this article, a dual metal surround gate junctionless transistor (DMSGJLT) was used to solve the Poisson equation using the parabolic approximation technique to model the electrostatic potential, threshold voltage, drain current, transconductance, drain-induced barrier lowering, power and delay predicted by the analytical solution.
Abstract: The 2-D analytical solution of electrostatic potential and enhanced drain current is modeled for a dual metal surround gate junctionless transistor (DMSGJLT) by solving the Poisson equation using the parabolic approximation technique. The gate engineered DMSGJLT produces an increase in the mobility of electrons in the channel. Enhancement in drain current of 35 $\mu \text{A}$ is obtained than single metal JLT for the same dimension. Due to that, the gain increases, short channel effects and leakage current decreases. The electrostatic potential, threshold voltage, drain current, transconductance, drain-induced barrier lowering, power and delay predicted by the analytical solution have excellent agreement with the simulation results obtained from Technology Computer-Aided Design. The analytical modeling provides useful insight on physics of short channel effects. The inverter circuit is implemented with a DMSGJLT and is compared with that of a single metal device. The noise margin analysis is made for the inverter circuit employing both dual metal and single metal devices. It is found that gate engineering improves the noise margin to a much extend and due to this, the voltage loss is also improved with a DMSGJLT.

28 citations

Patent
30 Nov 2001
TL;DR: In this paper, a new current reference circuit based on MOS transistors is presented, which does not depend upon the threshold voltage of the first and second transistors and can be used to create a nearly zero temperature coefficient current reference.
Abstract: A new current reference circuit is achieved. This current reference circuit is based on MOS transistors but does not depend upon the threshold voltage. The circuit comprises, first, a first MOS transistor having gate, drain, and source. A gate voltage value is coupled from the gate to the source. A second MOS transistor has gate, drain, and source. The second MOS transistor is of the same size and type as the first MOS transistor. The source is coupled to said first MOS transistor source. The gate voltage value plus a delta voltage value is coupled from the gate to the source. A means is provided for forcing a drain voltage value from the drain to the source of the first MOS transistor and from the drain to the source of the second MOS transistor. The first MOS transistor and the second MOS transistor conduct drain currents in the linear mode. Finally, a means is provided for subtracting the first MOS transistor drain current from the second MOS transistor drain current to thereby create a current reference value. The current reference value does not depend upon the threshold voltage of the first and second MOS transistors. The circuit may be further applied to create a nearly zero temperature coefficient current reference.

28 citations

Patent
25 Jun 2009
TL;DR: In this article, the inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses, where the driving transistor region is thinner than the channel region of the load transistor.
Abstract: The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel region of the load transistor. A channel layer of the driving transistor may have a recessed region between a source and a drain which contact both ends of the channel layer. The driving transistor may be an enhancement mode transistor and the load transistor may be a depletion mode transistor.

28 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202330
202279
202161
202055
201958
201845