Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Locos MOS device for ESD protection

Abstract: A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.

Short-channel effects and drain-induced barrier lowering in nanometer-scale GaAs MESFET's

Abstract: Short-channel effects in GaAs MESFETs are investigated. MESFETs were fabricated with gate lengths in the range of 40 to 300 nm with GaAs and AlGaAs buffer layers. The MESFETs were characterized by DC transconductance, output conductance, and subthreshold measurements. This work focuses on overcoming the short-channel effect of large output conductance by the inclusion of an AlGaAs buffer layer, and identifying the benefit the AlGaAs buffer affords for reducing subthreshold current, including the effect of drain-induced barrier lowering. The design yielded 300-nm gate-length MESFETs with excellent suppression of the major short-channel effects. >

Localization of Gate Bias Induced Threshold Voltage Degradation in a-Si:H TFTs

Abstract: This letter describes a method to identify the channel region of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) in which threshold voltage(Vth) degradation occurs. The TFTs are subjected to gate bias stress under different operating conditions. Asymmetry in the measured TFT drain current in the forward direction (same source and drain during stress and measurement) and reverse direction (interchanging the source and drain terminals) shows localization of the gate-voltage dependent Vth shift mechanism. Based on the observations, a charge-based expression for Vth shift is derived.

Method of making a high voltage implanted channel device for VLSI and ULSI processes

Abstract: A process for fabricating a high voltage CMOS transistor having a non-self aligned implanted channel which permits the operation of the device at high voltages. The non-self aligned implanted channel does not require alignment with the gate electrode of the CMOS device, but is accurately implanted early in the fabrication of the device through reliance on direct wafer stepper technology. As a result, the non-self aligned implanted channel does not require a high temperature drive, such that fabrication of the transistor is compatible with VLSI and ULSI processes, and the transistor can be up-integrated onto logic integrated circuits. Accuracy of the placement of the non-self aligned implanted channel provides for a shorter channel length, which enables the device to be highly area efficient while also increasing the current capability of the device. Furthermore, the transistor is characterized by a large field-induced avalanche breakdown voltage, enhanced by a thick gate oxide, a lightly doped drain, a field oxide region between the gate and the drain, and known field plating techniques.

Design Structures Incorporating Semiconductor Device Structures with Reduced Junction Capacitance and Drain Induced Barrier Lowering

Abstract: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.