Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Bottom source NMOS triggered zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS)

Abstract: A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer thereon The TVS device further includes a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate wherein the drain region interfaces with the body region constituting a junction diode and the drain region encompassed in the body region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal The gate may be shorted to the drain for configuring the BS-MOSFET transistor into a two terminal device with a gate-to-source voltage equal to a drain-to-source voltage The drain/collector/cathode terminal disposed on top of the trench gate turns on the BS-MOSFET upon application of a threshold voltage of the BS-MOSFET thus triggering the bipolar transistor for clamping and suppressing a transient voltage substantially near a threshold voltage of the BS-MOSFET

Current detector circuit and current mode switching regulator

Abstract: A current detector circuit detects a current supplied to a load and generates as a detection result a voltage corresponding to the detected current. A first p-channel transistor has a source connected to a power supply and a gate connected to a ground, and is configured to allow the passage therethrough of a current that is 1/N of a current flowing through a transistor which drives the load. A second p-channel transistor has a source connected to a drain of the first p-channel transistor, and a third p-channel transistor is connected to the load. A voltage mirror circuit has first and second terminals connected to respective drains of the second and third p-channel transistors. A n-channel transistor has a drain connected to the drain of the first p-channel transistor and outputs a source voltage as the detection result of the current detector circuit.

Distributive nature of gate current and negative transconductance in heterostructure field-effect transistors

Abstract: Experimental data showing that the dependence of the gate current on the drain voltage in enhancement-mode heterostructure field-effect transistors changes qualitatively when the gate voltage is varied from below to above threshold are presented. The data lead to the conclusion that for gate voltages higher than the threshold voltage and drain voltages larger than the drain saturation voltage, most of the potential drop occurs in a small region near the drain end of the channel. The gate current is distributed along the channel so that electrons in the channel are diverted toward the gate. A model is proposed that takes into account such a distribution of the gate current along the channel. The distributive nature of the gate current leads to negative transconductance in heterostructure field-effect transistors at high gate voltages. Negative transconductance reaching -125 mS/mm in 1- mu m gate devices is observed, and an equivalent circuit model is proposed that describes the dependence of the drain current on the gate voltage in good agreement with present experimental data. >

Driving circuit for electroluminescent display device and its related method of operation

Abstract: A gate of a driving transistor is set to a offset level corresponding to the threshold of the driving transistor by an initializing current flowing between a source and a drain of the driving transistor or a compensating transistor for the driving transistor. A conduction state of the driving transistor is set according to a gate voltage of the gate of the driving transistor that corresponds to a data signal and the threshold of the driving transistor. A current of which a level corresponds to the conduction state and of which the direction is opposite to the direction of the initializing current flows through driving transistor.

Field effect transistor having source and/or drain forming schottky or schottky-like contact with strained semiconductor substrate

Abstract: The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.