Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Reducing leakage current in a thin-film transistor with charge carrier densities that vary in two dimensions

Abstract: In the channel layer of a thin film transistor (TFT), a channel and its drain meet at a transition within a transition region. The channel extends in a first, or horizontal, dimension away from the drain and extends in a second, or vertical, dimension from a side away from the gate to a side toward the gate. The charge carrier densities in the transition region vary in the second dimension in a way that reduces leakage current, because the position of the maximum electric field is moved away from the gate and its magnitude is reduced. Variation of densities in the second dimension can be produced by high angle implantation of a dopant and a counterdopant, providing a transition region between the drain and the channel underneath the gate. Variation of densities in the second dimension can also be produced with non-angled implantation by a process in which a sidewall spacer offsets the drain, providing a transition region that is between the drain and the channel and that can be doped independently of the drain. In a symmetric TFT in which either channel lead can function as a drain, charge carrier densities can vary in the second dimension at the transitions between each channel lead and the channel.

MOS thin film transistor

Abstract: Reduction of parasitic coupling capacitances which are otherwise formed between conventional NMOS transistor N type drain regions and the transistor's substrate and well regions is described by using a semiconductor-on-insulator (SOI) substrate and forming the NMOS transistor on a semiconductor (Si) substrate having a buried insulator forming a deep, lightly doped N type subsurface region beneath the conventional surface drain region (but not the source region) which contacts the buried insulator.

Majority carrier power diode

Abstract: A power diode having substantially no reverse-recovery time and relatively high conductance. The power diode is a majority carrier semiconductor having a structure that is similar to that of a metal oxide semiconductor field effect transistor (MOSFET), in that it includes a source (38), a drain (38), a gate (42), and a body (36). In one embodiment, to increase conductance of the power diode, a linked-cell configuration that reverses the geometry of a conventional cell-type MOSFET is employed, thereby increasing the width of a conductance channel over that of a conventional MOSFET, and compensating for a relatively low level of inversion in the channel region. Negative and positive feedback circuits are used to further improve the conductance of the power diode by dynamically setting a bias voltage applied between the gate and the source to a level just below a threshold voltage.

A convergence scheme for over-erased flash EEPROM's using substrate-bias-enhanced hot electron injection

Abstract: A novel convergence scheme using substrate-bias-enhanced hot electron injection is proposed to tighten the cell threshold voltage distribution after erasure for stacked gate flash EEPROM's. By lowering the drain voltage and increasing the magnitude of the negative substrate bias voltage, the substrate current is reduced but the hot electron gate current is enhanced significantly, and the convergence time is shown to be more than a hundred times shorter than the previous scheme. With the convergence operation performed near the ON-OFF transition region of the cells, the total drain current for all the converged cells is reduced and low power consumption is achieved. >

Structure to reduce the on-resistance of power transistors

Abstract: A power transistor is disclosed that exhibits increased power capacity, reduced on-resistance and prevents current pinch off. The transistor comprises an insulated gate field-effect transistor and including a gate insulator; a protective region having a first conductivity type adjacent the insulator of the transistor for protecting the insulator from the degrading or breakdown effects of a large voltage applied across the device; and a current-enhancing layer having the opposite conductivity type from the protective region and positioned between the protective region and another first conductivity-type region of the transistor.