Topic
Drain-induced barrier lowering
About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.
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TL;DR: In this article, a novel resist etch-back process for fabrication of separated-gate four-terminal FinFETs has been investigated, which enabled co-fabrication of threeterminal and fourterminal (4T) fin-fets on a same chip.
Abstract: A novel resist etch-back process for fabrication of separated-gate four-terminal FinFETs has been investigates. This process enabled co-fabrication of three-terminal (3T) and four-terminal (4T) FinFETs on a same chip. The fabricated 3T-FinFET shows excellent sub-threshold characteristics and drain induced barrier lowering (DIBL) value whereas the 4T-FinFET provides efficient Vth controllability. The effective Vth controllability with keeping a small sub-threshold slope has been confirmed in the synchronized double gate (DD) operation mode
26 citations
Patent•
31 Jul 2001
TL;DR: In this article, the p-top layer is implanted through a thin gate oxide, and is being diffused into the silicon later in the process using the source/drain anneal process.
Abstract: A high voltage MOSFET device ( 100 ) has an nwell region ( 113 ) with a p-top layer ( 108 ) of opposite conductivity formed to enhance device characteristics. The p-top layer is implanted through a thin gate oxide, and is being diffused into the silicon later in the process using the source/drain anneal process. There is no field oxide grown on the top of the extended drain region, except two islands of field oxide close to the source and drain diffusion regions. This eliminates any possibility of p-top to be consumed by the field oxide, and allows to have a shallow p-top with very controlled and predictable p-top for achieving low on-resistance with maintaining desired breakdown voltage.
26 citations
Patent•
27 Feb 2001
TL;DR: In this article, an improved method and structure for a transistor device with a lateral drift region and a conducting top field plate is presented, which consists of decreasing the gate to drain capacitance by decreasing the portion of the field plate that is connected to the gate electrode, and hence the effective overlap of the gate with the drift region.
Abstract: An improved method and structure for a transistor device with a lateral drift region and a conducting top field plate is presented. The method consists of decreasing the gate to drain capacitance by means of decreasing the portion of the field plate that is connected to the gate electrode, and hence the effective overlap of the gate with the drift region and drain. This results in decreased energy dissipation in switching the transistor, and more efficient operation. The rate of decrease of the gate to drain capacitance is even faster at higher drain voltages, inuring in significant energy efficiencies in high voltage applications.
26 citations
Patent•
01 Oct 1999
TL;DR: In this paper, a method of forming an ETOX-cell in a semiconductor substrate is disclosed, which can be organized into a NOR array, but with no need of source line connections.
Abstract: A method of forming an ETOX-cell in a semiconductor substrate is disclosed. The method begins with forming a p-well in the substrate. Then, a drain region and a source region is formed in the p-well. The drain region is of a first dopant type and the source region is of a second dopant type (i.e. same as the dopant type of the p-well). A floating-gate and tunnel oxide stack is formed above the p-well, the floating gate formed between the drain region and the source region and only after the drain region and the source region have been formed. The floating gate is doped with the same dopant type as the p-well. Finally, a control gate is formed above the floating-gate, the floating-gate and the control gate separated by a dielectric layer. The new ETOX cells can be organized into a NOR array, but with no need of source line connections. Each cell is programmed by band-to-band induced substrate hot-electron (BBISHE) at the source, and read by GIDL at the drain side.
26 citations
Patent•
08 Sep 1993TL;DR: In this paper, a circuit in which the source-to-drain conduction path of a power switching transistor (N1) is connected in series with an inductive load (L1) between first and second power terminals is described.
Abstract: A circuit in which the source-to-drain conduction path of a power switching transistor (N1) is connected in series with an inductive load (L1) between first and second power terminals and includes a voltage transient clamping transistor (P1) having its source-to-drain conduction path connected between the drain and gate of the switching transistor (N1). In response to a turn-off signal applied to the gate of the switching transistor (N1), a transient voltage is generated at the drain of the switching transistor and when the transient voltage exceeds a predetermined value, the clamping transistor (P1) is turned on. The conduction of the clamping transistor (P1) limits the voltage rise at the drain of the switching transistor (N1) and tends to maintain the switching transistor (N1) conductive to aid in the discharge of the energy stored in the inductive load (L1). A unidirectional conducting element connected in series with the clamping transistor (P1) ensures that only current of a polarity to discharge the inductive load (L1) flows through the clamping transistor (P1).
26 citations