Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Field effect transistor for detection of biological reactions

Abstract: A field effect transistor including conventional source and drain electrodes employs, in the gate region, a layer of antibody specific to a particular antigen. An electrolyte solution such as 0.155 Normal sodium chloride atop the antibody layer provides a predetermined drain current versus drain voltage characteristic for the device. Replacement of the electrolyte solution with another electrolyte solution containing the antigen alters the charge of the protein surface layer due to the antigen-antibody reaction, thus affecting charge concentration in a semiconductor inversion layer in the transistor. The time rate of change of drain current thus provides a measure of the antigenic protein concentration in the replacement solution.

An AlN/Al0.85Ga0.15N high electron mobility transistor

Abstract: An AlN barrier high electron mobility transistor (HEMT) based on the AlN/Al0.85Ga0.15N heterostructure was grown, fabricated, and electrically characterized, thereby extending the range of Al composition and bandgap for AlGaN channel HEMTs. An etch and regrowth procedure was implemented for source and drain contact formation. A breakdown voltage of 810 V was achieved without a gate insulator or field plate. Excellent gate leakage characteristics enabled a high Ion/Ioff current ratio greater than 107 and an excellent subthreshold slope of 75 mV/decade. A large Schottky barrier height of 1.74 eV contributed to these results. The room temperature voltage-dependent 3-terminal off-state drain current was adequately modeled with Frenkel-Poole emission.

High-performance 50-nm-gate-length Schottky-source/drain MOSFETs with dopant-segregation junctions

Abstract: High-performance operation was achieved in a novel Schottky-source/drain MOSFET (SBT: Schottky barrier transistor), which has dopant-segregation (DS) Schottky source/drain. Sub-100 nm complementary DS-SBTs were fabricated using the CoSi/sub 2/ process, which was fully compatible with the current CMOS technology. Excellent CMOS performance was obtained without any channel-mobility degradation, and CMOS ring oscillator was successfully demonstrated. In addition, >20 % improvement in drive current over the conventional n-MOSFETs was confirmed in the n-type DS-SBTs around the gate length of 50 nm.

Experimental investigation of a PtSi source and drain field emission transistor

Abstract: A p‐type PtSi source and drain, no ‘‘gap,’’ metal oxide semiconductor field effect transistor (MOSFET) has been successfully fabricated and experimentally investigated in detail down to 4.2 K. Gate curves (source current versus gate voltage) clearly show that, in the ‘‘on’’ state, the current flow mechanism from the source metal into the channel gradually changes from primarily thermal emission over the small ∼0.2 eV Schottky barrier to holes to completely field emission through the triangular Schottky barrier as the temperature is lowered below ∼100 K. Gate curves for different channel lengths also show minimal short channel effects down to 1.0 μm, in agreement with previous simulations. Drain curves (source current versus drain voltage) demonstrate that the drive current is comparable to that of a conventional MOSFET, and that the Schottky barrier is rendered transparent to the flow of holes when the device is strongly ‘‘on.’’

Semiconductor memory device and method of reading out information for the same

Abstract: In a memory cell according to the present invention, when positive high voltages are respectively applied to a gate( 20 ) and a drain region( 14 ) and a source region( 13 ) is grounded, hot electrons are produced in the boundary between the drain region(14) and a channel(25). The hot electrons are locally injected into an insulation film(19), to be trapped therein. Consequently, information is written. At the time of reading out information, the drain region(14) is grounded, a positive read voltage is applied to the source region(13), and a predetermined sense voltage is applied to the gate(20). At this time, the area between the source and the drain is kept in a non-conduction state if electrons are stored in the insulation film(19), while conduction occurs between the source and the drain if no electrons are stored therein. Since the formation of the channel(25) in the vicinity of the drain region(14) is delayed at the time of reading, thereby to make it possible to increase a threshold voltage, therefore, information can be accurately read out. No hot electrons are produced in the boundary between the drain region(14) and the channel(25) at the time of reading, it is possible to effectively prevent so-called soft writing.