Topic
Drain-induced barrier lowering
About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.
Papers published on a yearly basis
Papers
More filters
TL;DR: In this article, a low-density drain high-electron mobility transistor (LDD-HEMT) was proposed to enhance the breakdown voltage and reduce current collapse. But the degradation of current cutoff frequency and power gain cutoff frequency was not addressed.
Abstract: We report a low-density drain high-electron mobility transistor (LDD-HEMT) that exhibits enhanced breakdown voltage and reduced current collapse. The LDD region is created by introducing negatively charged fluorine ions in the region between the gate and drain electrodes, effectively modifying the surface field distribution on the drain side of the HEMT without using field plate electrodes. Without changing the device physical dimensions, the breakdown voltage can be improved by 50% in LDD-HEMT, and the current collapse can be reduced. No degradation of current cutoff frequency (ft) and slight improvement in power gain cutoff frequency (fmax) are achieved in the LDD-HEMT, owing to the absence of any additional field plate electrode
108 citations
Patent•
23 Apr 1980
TL;DR: In this paper, the threshold voltage of both the channel and field regions of a MOSFET was controlled by forming a comparatively thick oxide film on a semiconductor surface, defining enhancement mode transistor regions in the oxide film to expose portions of the semiconductor surfaces, implanting p-type ions under conditions such that the peak distribution of ptype atoms lies in the semi-conductor substrate just beneath the semiconductors/oxide interface and counter-doping with n-type ion under conditions that no implanted ions penetrate the oxide films.
Abstract: A process is provided for fabricating MOSFET devices having field source, gate and drain regions. The threshold voltage of both the channel and field regions of such devices is controlled by forming a comparatively thick oxide film on a semiconductor surface, defining enhancement mode transistor regions in the oxide film to expose portions of the semiconductor surface, implanting p-type ions under conditions such that the peak distribution of p-type atoms lies in the semi-conductor substrate just beneath the semiconductor/-oxide interface and counter-doping with n-type ions under conditions such that no implanted ions penetrate the oxide film. As a consequence, a desirably high threshold voltage is obtained in the field region, while a desirably low threshold voltage is obtained in the channel region. Depletion mode transistors are fabricated on the same wafer by masking the enhancement mode regions, defining depletion mode transistor regions in the oxide film to expose portions of the semiconductor surface and implanting n-type ions under conditions such that no ions penetrate the mask or oxide film. Metal gate or refractory gate technology is then employed to fabricate source, gate and drain regions and electrical contacts thereto. Parasitic conduction paths between neighboring transistors are substantially eliminated due to the peak distribution of p-type atoms in the field region.
106 citations
Patent•
30 Dec 1999
TL;DR: In this article, the gate is doped with N-type material so that depletion regions are formed in the drift region when the gate voltage is equal to zero, and the depletion regions merge at the center of the mesa, pinching off the flow of current.
Abstract: In a trench-gated MOSFET, a lightly doped drift region of the N-type drain lies in the mesa between the trenches. The gate is doped with N-type material so that depletion regions are formed in the drift region when the gate voltage is equal to zero. The depletion regions merge at the center of the mesa, pinching off the flow of current when the device is turned off. This current-pinching effect allows the P-type body region to be made shallower and doped more lightly than usual without creating a punchthrough problem, because the barrier represented by the depletion regions adds to the normal current blocking capability of the PN junction between the body and drain regions. When the device is turned on by biasing the gate to a positive voltage, a low resistance accumulation layer forms in the drift region adjacent the trenches.
106 citations
Patent•
30 Sep 2003
TL;DR: In this article, a 1T/FB dynamic random access memory (DRAM) cell is provided that includes a field effect transistor fabricated using a process compatible with a standard CMOS process.
Abstract: A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region. A buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region. A bias voltage can be applied to the buried region, thereby controlling leakage currents in the 1T/FB DRAM cell.
106 citations
TL;DR: In this paper, the threshold voltages and read schemes of silicon nanocrystal memories with two bits per cell were examined by experiments and simulations, and it was found that the drain induced barrier lowering (DIBL) has a marked effect on Vth's in the four states and thus on read schemes for detecting the four Vths.
Abstract: The threshold voltages (Vth's) and read schemes of silicon nanocrystal memories with two bits per cell are examined by experiments and simulations. It is found that the drain induced barrier lowering (DIBL) has a marked effect on Vth's in the four states and thus on read schemes for detecting the four Vth's. It is also shown that the read scheme can be selected by controlling DIBL using device parameters including gate length, injected charge fraction, and injected charge density. Suitable read schemes for low-voltage and low-power applications are discussed.
106 citations