Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Exploring the novel characteristics of hetero-material gate field-effect transistors (HMGFETs) with gate-material engineering

Abstract: The novel characteristics of a new type of MOSFET, the hetero-material gate field-effect transistor (HMGFET), are explored theoretically and compared with those of the compatible MOSFET. Two conceptual processes for realizing the HMG structure are proposed for integration into the existing silicon technology. The two-dimensional (2-D) numerical simulations reveal that the HMGFET demonstrates extended threshold voltage roll-off to much smaller length and shows simultaneous transconductance enhancement and suppression of short-channel effects (SCEs) [drain-induced barrier-lowering (DIBL) and channel-length modulation (CLM)] and, more importantly, these unique features could be controlled by engineering the material and length of the gate. This work demonstrates a new way of engineering ultrasmall transistors and provides the incentive and guide for experimental exploration.

Threshold Voltage Instability in 4H-SiC MOSFETs With Phosphorus-Doped and Nitrided Gate Oxides

Abstract: Threshold voltage instability was investigated for 4H-SiC MOSFETs with phosphorus-doped (POCl3-annealed) and nitrided (NO-annealed) gate oxides. Threshold voltage shift observed in the bidirectional drain current–gate voltage characteristics was evaluated using various gate voltage sweeps at room and elevated temperatures up to 200 °C. The threshold voltage shift was also studied after applying positive and negative bias-temperature stress. Two types of MOSFETs showed different instability characteristics, depending on gate biases and temperatures. These features were found to originate from the difference in trap density and trap location at/near the oxide/SiC interface and in the oxide. It is apparent that the oxide traps in phosphorus-doped oxides and near-interface traps in nitrided oxides are the main origin of the threshold voltage instability via capture and emission (in the case of oxide traps, only capture) of both electrons and holes.

Circuit and method for programming charge storage memory cells

Abstract: A circuit and method for self-converging programming of a charge storage memory cell, such as NROM or floating gate flash, having a source and a drain in a substrate, a charge storage element and a control gate. The method includes applying source voltage, inducing a body effect that increases the effective threshold, and increasing the source voltage along with the drain voltage to moderate hot electron injection efficiency during the program operation, at least during a portion of the program operation in which convergence on a target threshold occurs. A selected gate voltage is applied during the operation to establish the target threshold voltage. In multiple bit cells, the gate voltage is set according to the data values to be stored, enabling self-convergence at more than one target threshold.

High voltage MOS transistors

Abstract: An insulated-gate, field-effect transistor and a double-sided, junction-gate field-effect transistor are connected in series on the same chip to form a high-voltage MOS transistor. An extended drain region is formed on top of a substrate of opposite conductivity-type material. A top layer of material having a conductivity-type opposite that of the extended drain and similar to that of the substrate is provided by ion-implantation through the same mask window as the extended drain region. This top layer covers only an intermediate portion of the extended drain which has ends contacting a silicon dioxide layer thereabove. The top layer is either connected to the substrate or left floating. Current flow through the extended drain region can be controlled by the substrate and the top layer, which act as gates providing field-effects for pinching off the extended drain region therebetween. A complementary pair of such high-voltage MOS transistors having opposite conductivity-type are provided on the same chip.

Titanium disilicide self-aligned source/drain + gate technology

Abstract: Silicides have been used to lower the resistance of gate level interconnects. Recently silicidation of source/drain diffusions have also been reported. In scaled CMOS devices, silicidation of source/drains is particularly important in reducing the sheet resistance of p+ source/drain diffusions. In this paper, a novel technique is described in which TiSi 2 is formed self-aligned to both source/drain and gate regions. Both n and p-channel MOSFETs Silicided with self-aligned TiSi 2 on source/drains gates have been fabricated using this technique. Sheet resistances below 5 Ω/□ on both gate and source/drain levels have been achieved and thus represent at least a 10X reduction in the resistance of p+diffusions. Diode leakage, subthreshold leakage, and threshold voltage measurements on silicided devices are comparable to that of control devices without silicidation, CMOS circuit applications of this TiSi 2 self-aligned source/drain and gate technology are discussed.