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Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.


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Journal ArticleDOI
TL;DR: In this article, a GaAs FET model suitable for SPICE circuit simulations is developed, where the dc equations are accurate to about 1 percent of the maximum drain current, and a simple interpolation formula for drain current as a function of gate-to-source voltage connects the square-law behavior just above pinchoff and the square root law for larger values of the drain current.
Abstract: We have developed a GaAs FET model suitable for SPICE Circuit simulations. The dc equations are accurate to about 1 percent of the maximum drain current. A simple but accurate interpolation formula for drain current as a function of gate-to-source voltage connects the square-law behavior just above pinchoff and the square-root law for larger values of the drain current. The ac equations, with charge-storage elements, describe the variation of the gate-to-source and gate-to-drain capacitances as the drain-to-source voltage approaches zero and when this voltage becomes negative. Under normal operating conditions the gate-to-source capacitance is much larger than the gate-to-drain capacitance. At zero drain-to-source voltage both capacitances are about equal. For negative drain-to-source voltages the original source acts like a drain and vice versa. Consequently the normally large gate-to-source capacitance becomes small and acts like a gate-to-drain capacitance. In order to model these effect it is necessary to realize that, contrary to conventional SPICE usage, there are no separate gate-to-source and gate-to-drain charges, but that there is only one gate Charge which is a function of gate-to-source and gate-to-drain voltages. The present treatment Of these capacitances permits simulations-in which the drain-to-source voltage reverses polarity, as occurs in pass-gate circuits.

520 citations

Journal ArticleDOI
TL;DR: In this article, the threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep submicrometer range has been investigated.
Abstract: The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >

466 citations

Journal ArticleDOI
TL;DR: In this paper, the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications is examined.
Abstract: This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

384 citations

Journal ArticleDOI
TL;DR: In this article, the GaN-based recessed MIS-gate structure in conjunction with negative polarization charges under the gate allows the high threshold voltage, whereas the low on-state resistance is maintained by the 2D electron gas remaining in the channel except for the recessed gate region.
Abstract: This letter reports normally-off operation of an AlGaN/GaN recessed MIS-gate heterostructure field-effect transistor with a high threshold voltage. The GaN-based recessed MIS-gate structure in conjunction with negative polarization charges under the gate allows us to achieve the high threshold voltage, whereas the low on-state resistance is maintained by the 2-D electron gas remaining in the channel except for the recessed MIS-gate region. The fabricated device exhibits a threshold voltage as high as 5.2 V with a maximum field-effect mobility of 120 cm2/Vmiddots, a maximum drain current of over 200 mA/mm, and a breakdown voltage of 400 V.

383 citations

Journal ArticleDOI
L.D. Yau1
TL;DR: A simple expression for the threshold voltage of an IGFET is derived from a charge conservation principle which geometrically takes into account two-dimensional edge effects in this paper, which is valid for short and long-channel lengths.
Abstract: A simple expression for the threshold voltage of an IGFET is derived from a charge conservation principle which geometrically takes into account two-dimensional edge effects. The expression is derived for zero drain voltage and is valid for short and long-channel lengths. The dependence of the threshold voltage on the source and drain diffusion depth, r j , and channel length, L , is explicitly given. In the limit, L / r j → ∞, the threshold voltage equation reduces to the familiar expression for the long-channel case. The theory is compared with the measured threshold voltages on IGFET's fabricated with 1·4, 3·8 and 7·4 μm channel lengths. The dependence of the threshold voltage under backgate bias voltages ranging from zero to breakdown agrees closely with the theory.

378 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202330
202279
202161
202055
201958
201845