Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Study of 1/f noise in N-MOSFET's: Linear region

Abstract: A modified McWhorter model has been developed to explain the mechanisms involved in the 1/f noise in n-channel metal-oxide, semiconductor field-effect transistors (MOSFET's). Under the assumption of an energy distribution of traps in the bandgap, an expression for the power spectral density of 1/f noise was derived for MOSFET's operating in the linear region. Experimentally, noise measurements were performed on short-channel enhancement-mode MOSFET's with gate widths of 100 µm, and varying gate lengths of 2 to 10 µm. It was found that noise power increased with increasing drain voltage or decreasing gate bias. Quantitative analyses have been done to compare the experimental results with the model calculations.

Semiconductor memory device with floating storage bulk region and method of manufacturing the same

Abstract: A memory cell MC comprises one MOS transistor having a floating bulk region which is electrically isolated from others. A gate electrode 13 of the MOS transistor is connected to a word line WL, a drain diffusion region 14 thereof is connected to a bit line BL, and a source diffusion region 15 thereof is connected to a fixed potential line SL. The memory cell stores a first threshold state in which majority carriers produced by impact ionization are injected and held in the bulk region 12 of the MOS transistor and a second threshold state in which the majority carriers in the bulk region 12 of the MOS transistor are emitted by a forward bias at a pn junction on the drain side as binary data. Thereby, a semiconductor memory device in which a simple transistor structure is used as a memory cell, enabling dynamic storage of binary data by a small number of signal lines can be provided.

Drain Work Function Engineered Doping-Less Charge Plasma TFET for Ambipolar Suppression and RF Performance Improvement: A Proposal, Design, and Investigation

Abstract: A novel device configuration is presented for doping-less charge plasma tunnel FET (TFET) for suppression of ambipolar nature with improved high-frequency figures of merit. For this, the drain electrode, which is used to induce n+ drain region, is separated into two sections of high and low work functions. The work function of the drain electrode section near to channel is considered relatively higher than other part for restricting the tunneling of holes at drain/channel interface for negative gate bias. This concept creates asymmetrical charge carrier concentration in the drain region, which increases the tunneling width at the drain/channel interface. Therefore, the proposed device offers better performance in terms of ambipolar current, parasitic capacitance, and RF parameters. In this regard, a comparative study of the proposed device is performed with conventional and dual-metal gate doping-less TFETs. Furthermore, the optimization of the length and higher work function of the drain electrode near to channel is discussed in detail for the proposed device. Apart from above-mentioned advantages, the doping-less nature of the proposed device provides fabrication simplicity and immunity against random dopant fluctuations in comparison with the physically doped TFET.

Surface-Potential-Based Drain Current Model for Long-Channel Junctionless Double-Gate MOSFETs

Abstract: A surface-potential-based model is developed for the symmetric long-channel junctionless double-gate MOSFET. The relationships between surface potential and gate voltage are derived from some effective approximations to Poisson's equation for deep depletion, partial depletion, and accumulation conditions. Then, the Pao-Sah integral is carried out to obtain the drain current. It is shown that the model is in good agreement with numerical simulations from subthreshold to saturation region. Finally, we discuss the strengths and limitations (i.e., threshold voltage shifts) of the JLFET, which has been recently proposed as a promising candidate for the JFET.

Impact of fin width on digital and analog performances of n-FinFETs

Abstract: This paper examines the impact of an important geometrical parameter of FinFET devices, namely the fin width. From static and low-frequency measurements on n-FinFETs ( I – V , C – V and 1/ f noise), transistor Figures of Merit in the near-threshold region (like threshold voltage, subthreshold slope, and drain induced barrier lowering); linear region (mobility, series resistance, 1/ f noise) and saturation region (normalized transconductance, early voltage) are analyzed as a function of fin width. In the near-threshold region, fin width is seen to strongly impact the coupling between the back and front gates, while in the above threshold region, the most important impact of fin width is on the parasitic source/drain resistance, which affects different strong inversion parameters to different extents. With the help of analytical expressions, the impact of series resistance on these device parameters is studied, and the contribution from series resistance is de-embedded, enabling extraction of intrinsic device parameters. Significant differences are observed between the intrinsic and extrinsic parameters, especially for short and narrow devices, which also underlines the need for accounting for series resistance effects at every stage of FinFET characterization.