Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Field effect transistor and method for manufacturing the same

Abstract: A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.

Fabrication method for sub-half micron CMOS transistor

Abstract: A technique for forming a high-performance sub-half micron MOS transistor is disclosed which has improved short channel characteristics without degradation of device performance. The transistor comprises a semiconductor substrate, a gate electrode, graded source and drain impurity regions, a first set of gate sidewall spacers, and a second set of gate sidewall spacers. The graded source and drain impurity regions comprise a relatively linear continuum of doped regions, ranging from lightly doped (LDD) regions, to moderately doped (MDD) regions, to heavily doped regions. Additionally, the transistor may include a punch through barrier region located within the substrate under the gate electrode. With these features, the transistor of the present invention allows for more precise control of conduction channel length without degradation of either (1) body factor and current drive, and/or (2) junction leakage, and without compromising hot carrier immunity.

MOSFET with reduced short channel effect

Abstract: An MOSFET provided with a gate insulating film formed on a semiconductor surface between a source region and a drain region, a gate electrode formed on the gate insulating film, and a channel region sandwiched between the source region and the drain region and made up of a first layer and a second layer is disclosed in which the first layer lies beneath the gate insulating film and is opposite in conductivity type to the source and drain regions, the second layer lies beneath the first layer and has the same conductivity type as the source and drain regions, and the length of the second layer between the source region and the drain region is greater than the length of the first layer between the source region and the drain region.

Voltage translation and overvoltage protection

Abstract: A voltage translator is provided that translates a lower voltage to a higher voltage, for example, a 3.3V voltage to a 5.0V voltage. The 3.3V voltage is received on source/drain terminal N1 of an NMOS transistor (130). The transistor gate is at 3.3V. The other source/drain terminal N2 of the transistor (130) is connected to an input of a CMOS inverter (138) powered by 5.0V. The inverter output is connected to the gate of a PMOS transistor connected between 5.0V and terminal N2. The PMOS transistor pulls terminal N2 to 5.0V when terminal N1 is at 3.3V. The same translator is suitable for translating a 5.0V voltage on terminal N1 to 3.3V on terminal N2 if the inverter is powered by 3.3V and the PMOS transistor is connected betwween 3.3V and terminal N2. Also, an output driver is provided in which a voltage protection circuitry prevents charge leakage from the driver output terminal to the driver's power supply when the voltage on the bus connected to the output terminal exceeds the power supply voltage.

Double gate trench transistor

Abstract: A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.