Topic
Drain-induced barrier lowering
About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.
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TL;DR: In this article, the authors demonstrate that careful control of the semiconductor-insulator interface state densities is essential to VT and VFB control and the fabrication of reliable OFET integrated circuits.
Abstract: Charged interface states are introduced by UV-ozone treatment of a polymer gate dielectric, parylene, prior to deposition of the organic semiconductor, pentacene, thereby modifying the organic field effect transistor (OFET) operation from enhancement to depletion mode. Quasistatic capacitance-voltage measurements and the corresponding current-voltage characteristics show that the threshold voltage VT and flatband voltage VFB can be shifted by over +50V, depending on the ozone exposure time. This work demonstrates that careful control of the semiconductor-insulator interface state densities is essential to VT and VFB control and the fabrication of reliable OFET integrated circuits.
86 citations
09 May 1993
TL;DR: In this paper, transient threshold voltage shifts are characterized with respect to their dependence on stress amplitude and duration, relaxation time, gate bias, substrate bias, drain voltage, temperature, and channel width and length.
Abstract: MOSFETs subjected to large-signal gate-source voltage pulses on microsecond to millisecond time scales exhibit transient threshold voltage shifts which relax over considerably longer periods of time. This problem is important in high-accuracy analog circuits where it can cause errors at the 12 b level and above. In this paper, transient threshold voltage shifts are characterized with respect to their dependence on stress amplitude and duration, relaxation time, gate bias, substrate bias, drain voltage, temperature, and channel width and length. In contrast to previous studies, threshold voltage shifts are measured at time and voltage scales relevant to analog circuits, and are shown to occur even when the effects of Fowler-Nordheim tunneling, avalanche injection, hot carriers, trap generation, self-heating, mobile ions, and dipolar polarizations are absent. A new model is proposed in which channel charge carriers tunnel to and from near-interface oxide traps by one of three parallel pathways. Transitions may occur elastically, by direct tunneling between the silicon band edges and an oxide trap, or inelastically, by tunneling in conjunction with a thermal transition in the insulator or at the Si-SiO/sub 2/ interface. Simulations based on this model show excellent agreement with experimental results. The threshold voltage shifts are also shown to be correlated with 1/f noise, in corroboration of the tunneling model. Techniques for the minimization and modeling of errors in circuits are presented. >
86 citations
Patent•
12 Feb 1987
TL;DR: In this paper, the Schottky barrier gate field effect transistor (SGFE transistor) was proposed, where the gate electrode is fixed to an insulative portion formed on the channel region.
Abstract: This Schottky barrier gate field effect transistor has N + -type source and drain regions formed in the surface area of a GaAs semi-insulation substrate, a channel region formed between the source and drain regions, and a gate electrode formed on this channel region. Particularly, in this Schottky barrier gate field effect transistor, the gate electrode has a first metal portion, which is preferably in Schottky contact with the channel region, and a second metal portion, which stably affixes to the first metal portion. The first and second metal portions are fixed to an insulative portion formed on the channel region.
86 citations
TL;DR: In this article, the effect of the choice of the source and drain contact metal is investigated for both top and bottom-contact device structures, and the results of two-dimensional electrostatic modeling of organic field effect transistors, focusing on the formation of the conductive channel, are reported.
Abstract: Results of two-dimensional electrostatic modeling of organic field-effect transistors, focusing on the formation of the conductive channel, are reported. The effect on channel formation of the choice of the source and drain contact metal is investigated for both top- and bottom-contact device structures. High-work-function metal (e.g., gold) source and drain contacts produce a conducting p-type region near these contacts. In contrast, low-work-function metal source and drain contacts (e.g., magnesium) lead to depleted regions. In the center of the device, between the source and drain contacts, the channel carrier density at a fixed gate bias is determined by the work function of the gate contact material, and is essentially independent of the metal used to form the source and drain contacts. The principal difference between top- and bottom-contact structures is the spatial variation of the charge density in the vicinity of the source and drain contacts. The channel carrier density for a fixed gate bias (a...
85 citations
Patent•
IBM1
TL;DR: In this article, a self-aligned source and drain contacts with Schottky metal-to-semiconductor junction and a T-shaped gate were used to make a field effect transistor.
Abstract: A field effect transistor and method for making is described incorporating self aligned source and drain contacts with Schottky metal-to-semiconductor junction and a T-shaped gate or incorporating highly doped semiconductor material for the source and drain contacts different from the channel material to provide etch selectivity and a T-shaped gate or incorporating a metal for the source and drain contacts and the oxide of the metal for the gate dielectric which is self aligned. The invention overcomes the problem of self-aligned high resistance source/drain contacts and a high resistance gate electrode for submicron FET devices which increase as devices are scaled to smaller dimensions.
85 citations