Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

A New Quasi-2-D Threshold Voltage Model for Short-Channel Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs

Abstract: Based on the quasi-2-D scaling equation, a new threshold voltage model for short-channel junctionless (JL) cylindrical surrounding gate (JLCSG) MOSFETs is developed. The model explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage behavior. The model can also be extendable to its counterpart of junction-based cylindrical surrounding gate (JBCSG) MOSFETs. The model is verified by its calculated results matching well with those of the 3-D numerical simulator and can be easily used to explore the threshold voltage characteristics of JLCSG MOSFETs for its simple formula and computational efficiency.

Accumulation field effect microelectronic device and process for the formation thereof

Abstract: A gated microelectronic device is provided that has a source with a source ohmic contact with the source characterized by a source dopant type and concentration. A drain with a drain ohmic contact with the drain characterized by a drain dopant type and concentration. An intermediate channel portion characterized by a channel portion dopant type and concentration. An insulative dielectric is in contact with the channel portion and overlaid in turn by a gate. A gate contact applies a gate voltage bias to control charge carrier accumulation and depletion in the underlying channel portion. This channel portion has a dimension normal to the gate which is fully depleted in the off-state. The dopant type is the same across the source, drain and the channel portion of the device. The device on-state current is determined by the doping and, unlike a MOSFET, is not directly proportional to device capacitance.

Experimental Study Of Threshold Voltage Fluctuations Using An 8k MOSFET's Array

Abstract: Increasing the number of transistors and scaling down the dimensions of the transistors in ULSIs are considered to enhance the fluctuations of the transistor characteristics, from the viewpoint of the channel doping fluctuations [l], 121. However, the statistical study of the transistor fluctuations has not been experimentally performed. In this paper, we have focussed on the threshold voltage V,, fluctuatioris of 8k NMOSFET’s in a less than 0.8mm2 area, using a newly developed 256x32 transistor array with a 8bit binary counter. It is experimentally shown for the first time that the V,, fluctuatioris depend on the channel length and the gate oxide thiclmess. Furthermore, it is directly demonstrated that the V,, fluctuations correlate with the dopant number fluctuations of the channel region.

The variable threshold transistor, a new electrically-alterable, non-destructive read-only storage device

Abstract: A memory element has been developed that has the structure of a typical silicon planar p-channel enhancement insulated-gate field-effect transistor (IGFET). The information is stored by setting the threshold voltage of the IGFET to a high or low value. Interrogation is accomplished by applying a gate voltage intermediate to the threshold voltage extremes. Current will flow between source and drain if the recorded threshold voltage is less negative than the interrogating gate voltage; none will flow if the recorded threshold voltage is more negative. A high (negative) threshold voltage is written by applying a pulse of -50 v or higher for a duration of 1 msec or less between gate and substrate. A low threshold voltage is similarly obtained with positive 50 v pulse. The persistence of stored information has been demonstrated for periods of at least several months.

Cross coupled thin film transistors and static random access memory cell

Abstract: A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed in the second polysilicon layer. A dielectric layer is interposed between the first and second polysilicon layers. The first TFT gate overlaps the second TFT drain region in the first polysilicon layer and the second TFT gate overlaps the first TFT drain region in the second polysilicon layer. In another aspect of the invention, two TFTs are incorporated into a SRAM memory cell. The memory cell includes: (i) a bit line; (ii) an access transistor having a first source/drain and a second source/drain, the first source/drain being electrically connected to the bit line; (iii) a parasitic diode formed between the second source/drain of the access transistor and the substrate; (iv) a pull down transistor having a source, drain, channel and gate; (v) a first TFT having a source, drain, channel and gate, the first TFT gate being coupled to a power supply voltage V cc through an active load device comprising a second TFT having a source, drain, channel and gate, and to a voltage not greater than ground through the pull down transistor; and (vi) a storage node for storing a high voltage representative of a first digital data state or a low voltage representative of a second digital state, the storage node being coupled to the bit line through the access transistor, to the substrate through the parasitic diode, to the pull down transistor gate and to the power supply voltage V cc through the first TFT.