Topic
Drain-induced barrier lowering
About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.
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Patent•
21 Jun 2002TL;DR: In this article, a write-once-read-only memory cell with charge trapping in the gate insulator is described, and a bitline is coupled to the second source/drain region.
Abstract: Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. A plug couples the first source/drain region to an array plate. A bitline is coupled to the second source/drain region. The MOSFET can be programmed by operation in a reverse direction trapping charge in the gate insulator adjacent to the first source/drain region such that the programmed MOSFET operates at reduced drain source current when read in a forward direction.
71 citations
Patent•
05 Jul 1996TL;DR: An asymmetric halo implant provides a pocket region located under a device's source or drain near where the source (or drain) edge abuts the device's channel region as discussed by the authors, which has the same conductivity type as the device bulk (albeit at a higher dopant concentration).
Abstract: Low threshold voltage MOS devices having asymmetric halo implants are disclosed herein. An asymmetric halo implant provides a pocket region located under a device's source or drain near where the source (or drain) edge abuts the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. Only the source or drain, not both, have the primary pocket region. An symmetric halo device behaves like two pseudo-MOS devices in series: a "source FET" and a "drain FET." If the pocket implant is located under the source, the source FET will have a higher threshold voltage and a much shorter effective channel length than the drain FET.
71 citations
TL;DR: In this article, a 3D analytical modeling of SOI multigate (GAA), triple-gate (TG), double-gate and double-Gate (DG) FinFETs is presented.
71 citations
Patent•
12 Sep 2000
TL;DR: In this article, a transistor adapted to be used in an active-matrix liquid-crystal display is made larger than the length of the gate electrode taken in the longitudinal direction of the channel.
Abstract: A transistor adapted to be used in an active-matrix liquid-crystal display, the channel length, of the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric fields is applied to these offset regions from the gate electrode.
71 citations
TL;DR: It is observed that a suitably designed DMG AlGaN/GaN HEMT can considerably improve the linearity performance and minimize intermodulation distortion due to reduced drain induced barrier lowering and high-field effect; and a more uniform electric field for applications in 3-G mobile communication and low noise amplifiers.
71 citations