Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

FET having gate insulating film of nonuniform thickness and asymmetrical source and drain structures

Abstract: A high withstand voltage transistor and a method for manufacturing the same are disclosed. The transistor includes a semiconductor substrate, a field oxide film, a channel region formed of first and second channel regions each having a different concentration level, a gate insulating film having a step difference, a gate electrode having a step difference, a drain region including first, second, and third impurity regions, a source region including first and third impurity regions, a spacer, an interlayer dielectric film and a metal electrode. Threshold voltage can be maintained to an appropriate level, junction break voltage can be increased, and the punchthrough characteristic can also be enhanced.

Write operation for capacitorless RAM

Abstract: A method for writing data to single-transistor capacitorless (1T/0C) RAM cell, wherein the cell structure is predicated on an SOI MOS transistor that has a floating body region (12). Data is written to the cell by the instigation of band-to-band tunneling (BTBT) and the resulting generation of hole/electron pairs. Electrons are drawn from the body region through forward-biased drain (14) and source (15) regions so that holes accumulate in the body region. The increase in threshold voltage, caused by the accumulation of holes, may be defined and detected as a logic level (ONE, for example). In one embodiment, a split biasing scheme applies substantially identical voltages to the drain and to the source and a negative bias to the gate. In alternative embodiments, a negative gate bias is not required and the drain and source bias voltages may be offset so as to mitigate source damage.

Light emission and burnout characteristics of GaAs power MESFET's

Abstract: In order to obtain information on the field distributions and weak places of GaAs power MESFET's, the light emission and pulse burnout characteristics were investigated. Their dependence on the drain structure was also studied. The light emission occurs at the drain edge of the active region when the gate bias is zero volt, slightly changing its place depending on the drain structure. The drain edge of the epitaxial layer was also damaged by the pulse burnout experiments at zero gate bias. When the gate bias is increased, the light emission at the drain edge decreases rapidly until the gate Schottky breaks down and begins to give the light emission at the gate edge. The pulse burnout experiments suggest that the burnout initiates inside of the active or buffer epitaxial layer when the gate bias is near the pinchoff voltage.

Soi device with reduced drain induced barrier lowering

Abstract: A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the p- and n-wells of the SOI wafer. Backend high temperature processing steps induce diffusion of the boron and phosphorus contained in the BPSG into the p- and n-wells, thereby forming a retrograde dopant profile in the wells. The retrograde dopant profile reduces DIBL and also provides recombination centers adjacent the insulator layer and the active layer to thereby reduce floating body effects for the CMOS device.

Field effect transistor and CMOS element having dopant exponentially graded in channel

Abstract: A field effect transistor is fabricated on an SOI substrate. N-type source and drain regions are arranged apart from each other in a semiconductor thin film of the SOI substrate. A P-type channel region is formed between the source and drain regions. Moreover, a gate electrode is formed over the channel region to cover the channel region through a gate oxide film. Extreme portions of the channel region, adjacent to the source and drain regions, have higher doping concentrations than in a center portion thereof. Furthermore, the gradient of the doping profile in the channel region is adjusted so as to reduce the current gain of a parasitic transistor in the field effect transistor. This structure enables a reduction of the channel length of the field effect transistor to the sub-half-micron order without deteriorating the electrical characteristics of the field effect transistor.