Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Stable substrate bias generator for MOS circuits

Abstract: A circuit for controlling substrate bias voltage of a MOS semiconductor substrate. A first level detector monitors the substrate voltage and when the substrate bias falls below a threshold value, the first level detector couples an oscillator to cause a charge pump to pump charges into the substrate until the threshold level is again reached. A second detector operates as an excess negative voltage detector. This second detector monitors the substrate and when the bias voltage exceeds a predetermined limit, the second detector activates a clamper which drives the substrate toward ground potential until the bias voltage is again under the predetermined limit. By this technique the substrate bias is kept between the first threshold level and the maximum limit level. The first and second detectors are comprised of two transistor circuits, wherein the first leg is comprised of a depletion transistor and at least one enhancement transistor coupled between the supply voltage and the substrate. The second leg is comprised of two depletion transistors coupled between the supply voltage and its return. The junction of the depletion and the enhancement transistor of the first leg is coupled to the gate of one of the depletion transistors in the second leg such that the second leg is biased by the voltage on the junction of the transistors of the first leg which monitors the substrate voltage. The two legs determine the activation point of the detectors. The second detector is made to have at least one more enhancement transistor than the first detector to establish the limit level to be above that of the threshold level.

Method of forming a multiple implant lightly doped drain (MILDD) field effect transistor

Abstract: A multiple implant lightly doped drain ("MILDD") field effect transistor is disclosed. The transistor includes a channel, a gate, a dielectric structure that separates the gate from the channel, a source region and a drain region. The drain region has a first drain subregion, a second drain subregion and a third drain subregion. Each drain subregion has a dopant concentration that differs from that of the other two drain subregions. A method of forming the same is also disclosed.

Output buffer with improved ESD protection

Abstract: An output buffer having improved ESD tolerance is disclosed. The output buffer according to the invention incorporates a field oxide, or other high threshold voltage transistor, having its source-to-drain path connected between ground and the gate of the pull-down transistor, and has its gate connected to the output terminal. The threshold voltage of the high threshold device is greater than the power supply voltage, so as not to turn on during normal operation, but is lower than the BVCBO of the parasitic bipolar transistor associated with the pull-down transistor. The high threshold voltage device turns on with a positive voltage above its threshold appearing at the output terminal, such as occurs in an ESD event, resulting in the gate of the pull-down transistor being biased to ground. This causes the bipolar conduction, and the associated localized J-E heating, to take place away from the surface of the semiconductor, and away from the metal or silicide layers which provide the source of material for melt filaments. A similar high threshold transistor may be provided for biasing the gate of a pull-up transistor to the power supply terminal, having the same effect in the event of an ESD pulse positive relative to the power supply terminal. The high threshold transistors may be constructed as field oxide transistors, and preferably have large channel width-to-length ratios for fast switching.

High voltage ESD protection circuit with low voltage transistors

Abstract: An ESD protection circuit includes a stacked NMOS transistor pair coupled between a pad and a negative voltage supply, with a first transistor's drain connected to the pad and a second transistor's source connected to the negative power supply. A first voltage divider provides reduced voltage from a high voltage positive power supply to a gate of the first transistor, a first diode string coupled between the gates of the first and second transistors, a second diode string with its anode coupled to the pad, an inverter with a source of its PMOS transistor coupled to a cathode of the second diode string and with its NMOS transistor coupled to the negative power supply, an output node of the inverter coupled to a gate of the second transistor, and a RC circuit coupled to an input node of the inverter, for dissipation of ESD current.

Power MOS transistor

Abstract: A new and improved power MOS transistor having a protective diode with an increased breakdown voltage difference and less sheet resistivity is disclosed. In an up-drain type MOSFET, an n-type well layer has its top surface in which an elongated p-type base region is provided adjacent to a deep n + -type region (drain region). The p-type base region is formed so that it partly overlaps the deep n + region. A p + -type region (p-type base region) is connected to a source electrode. A surge bypassing diode D 1 is thus formed between the source and drain of the MOSFET.