Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Switch mode power supply with reduced switching losses

Abstract: The invention relates to a switching transistor presenting reduced switching losses. In the switching transistor, output capacitance is very high when drain/source voltages are low. As the drain/source voltage increases, the capacitance falls to such low values that the energy stored in the transistor becomes very low.

Device design considerations for ion implanted n-channel MOSFETs

Abstract: Device design considerations are presented for ion implanted, n-channel, polysilicon gate, enhancement-mode MOSFETs for dynamic switching applications. A shallow channel implant is used to raise the magnitude of the gate threshold voltage while also maintaining a low substrate sensitivity (i.e., without substantially increasing the dependence of the threshold voltage on the source-to-substrate "backgate" bias). Design trade-offs between channel implantation energy and dose and substrate bias were examined using both computer analyses and experimental devices. The design objective was to identify the combination of these three parameter values that gives both a low substrate sensitivitya nd a steep subthreshold conduction characteristic under the conditions of a gate threshold voltage of 1 V and a substrate bias range of 0 to -1 V. One-dimensional and two-dimensional computer analyses were performed to predict the effect of the device parameters on the electrical characteristics. MOSFETs were then fabricated to investigate the extremes of the design parameter range, and the experimental and predicted device characteristics were compared. An enclosed device structure proved particularly useful in evaluating the subthreshold characteristic at very low values of drain current.

Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation

Abstract: A flash memory having over-erased cells eliminated and comprising adjustable erase and program conditions. The maximum and minimum threshold voltages of the cells are measured during the whole erase and program operations. The over-erased cells are shut down by applying a word line voltage lower than the minimum threshold voltage measured previously. Pre-program and repair operations for the over-erased cell are eliminated. Low read voltage is achieved. The erase and program conditions for the gate, source, drain voltage, width of a pulse, and number of pulses are adjustable in accordance with the threshold voltage to optimize the performance. A lookup table stores the relevant gate, source, drain voltage, width of a pulse, and number of pulses with respect to the threshold voltage for the adjustable conditions. The benefits achieved by the operation of the flash memory include high efficiency, long endurance, narrow threshold voltage distribution, low power consumption, and low process-sensitivity.

Metal oxide semiconductor transistors having a drain punch through blocking region and methods for fabricating metal oxide semiconductor transistors having a drain punch through blocking region

Abstract: Metal oxide semiconductor transistors and devices with such transistors and methods of fabricating such transistors and devices are provided. Such transistors may have a silicon well region having a first surface and having spaced apart source and drain regions therein. A gate insulator is provided on the first surface of the silicon well region and disposed between the source and drain regions and a gate electrode is provided on the gate insulator. A region of insulating material is disposed between a first surface of the drain region and the silicon well region. The region of insulating material extends toward but not to the source region. A source electrode is provided that contacts the source region. A drain electrode contacts the drain region and the region of insulating material.

Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologies

Abstract: A method for forming a CMOS integrated circuit device, the method including; providing a semiconductor substrate, forming a gate layer overlying the semiconductor substrate, patterning the gate layer to form NMOS and PMOS gate structures including edges; forming a first dielectric layer overlying the NMOS and PMOS gate structures to protect the NMOS and PMOS gate structures including the edges, forming a first masking layer overlying a first region adjacent the NMOS gate structure; etching a first source region and a first drain region adjacent to the PMOS gate structure using the first masking layer as a protective layer for the first region adjacent the NMOS gate structure, and depositing a silicon germanium material into the first source and drain regions to cause the channel region between the first source and drain regions of the PMOS gate structure to be strained in a compressive mode.