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Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.


Papers
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Journal ArticleDOI
TL;DR: In this article, a drain-current model for undoped symmetric double-gate MOSFETs is proposed, where channel-length modulation and drain-induced barrier lowering are modeled by using an approximate solution of the 2D Poisson equation.
Abstract: A drain-current model for undoped symmetric double-gate MOSFETs is proposed. Channel-length modulation and drain-induced barrier lowering are modeled by using an approximate solution of the 2D Poisson equation. The new model is valid and continuous in linear and saturation regimes, as well as in weak and strong inversions. Excellent agreement was found with Silvaco-ATLAS simulations.

65 citations

Patent
08 Mar 2007
TL;DR: In this paper, an inner field-plate is disposed between the gate and drain of a gallium nitride high electron mobility transistor to reduce a peak value and to reduce gate leakage current while maintaining high frequency performance.
Abstract: A gallium nitride high electron mobility transistor, in which an inner field-plate is disposed between the gate and drain of the high electron mobility transistor, so that an electric field is distributed between gate and drain regions to reduce a peak value and to reduce gate leakage current while maintaining high frequency performance, thus obtaining a high breakdown voltage, reducing the capacitance between the gate and the drain attributable to a shielding effect, and improving linearity and high power and high frequency characteristics through variation in the input voltage of the inner field-plate.

65 citations

Patent
30 Mar 2011
TL;DR: In this paper, a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region there between, an insulating layer over the channel region, and a gate portion of the insulating layers.
Abstract: Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them.

65 citations

Journal ArticleDOI
TL;DR: In this article, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs is proposed.
Abstract: In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient ( d ), (ii) spacer width ( s ), (iii) spacer to doping gradient ratio ( s / d ) and (iv) silicon film thickness ( T si ), on short channel effects – threshold voltage ( V th ) and subthreshold slope ( S ), on-current ( I on ), off-current ( I off ) and I on / I off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG SOI devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below.

64 citations

Proceedings ArticleDOI
Kaushik Roy1
07 Sep 1998
TL;DR: In this article, the authors present different design techniques such as multiple threshold voltage, dynamic threshold control, substrate biasing, and leakage control using transistor stacking to achieve large improvements in leakage power during both stand-by and active mode of operation.
Abstract: Lowering supply voltage is one of the most effective ways of reducing power dissipation. Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between the leakage current and the transistor threshold voltage in the weak inversion region, static current (and hence, static power power dissipation) can no longer be ignored. In this paper the author presents different design techniques such as multiple threshold voltage, dynamic threshold control, substrate biasing, and leakage control using transistor stacking to achieve large improvements in leakage power during both stand-by and active mode of operation.

64 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202330
202279
202161
202055
201958
201845