scispace - formally typeset
Search or ask a question
Topic

Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.


Papers
More filters
Patent
13 Nov 2000
TL;DR: In this article, the threshold voltage of the drive transistor is set not to be smaller than the threshold voltages of the conversion transistor, and thereby a leakage current flowing through the light emitting device is suppressed.
Abstract: Each of picture elements comprises an input transistor for accepting a signal current from a data line when a scanning line is selected, a conversion transistor for converting the signal current into a voltage and for holding thus converted voltage, and a drive transistor for driving a light emitting device with drive current corresponding to the converted voltage. The conversion transistor flows the signal current to its channel to generate the voltage corresponding to the converted voltage and a capacitor to restrain the generated voltage. Further the drive transistor flows the drive current corresponding to the voltage stored in the capacitor. In this case the threshold voltage of the drive transistor is set not to be smaller than the threshold voltage of the conversion transistor, and thereby a leakage current flowing through the light emitting device is suppressed.

272 citations

Journal ArticleDOI
TL;DR: In this article, the authors demonstrated that overlapping the gate on the drain can suppress the ambipolar conduction, which is an inherent property of a tunnel field effect transistor (TFET).
Abstract: In this paper, we have demonstrated that overlapping the gate on the drain can suppress the ambipolar conduction, which is an inherent property of a tunnel field effect transistor (TFET). Unlike in the conventional TFET where the gate controls the tunneling barrier width at both source-channel and channel-drain interfaces for different polarity of gate voltage, overlapping the gate on the drain limits the gate to control only the tunneling barrier width at the source-channel interface irrespective of the polarity of the gate voltage. As a result, the proposed overlapping gate-on-drain TFET exhibits suppressed ambipolar conduction even when the drain doping is as high as \(1 \times 10^{19}\) cm \(^{-3}\) .

251 citations

Journal ArticleDOI
28 Jan 2014-ACS Nano
TL;DR: It is found that the contact resistivity for metal/MoS2 junctions is defined by contact area instead of contact width, which may reduce the influence of large contact resistance for MoS2 Schottky barrier transistors at the channel length scaling limit.
Abstract: In this article, we study the properties of metal contacts to single-layer molybdenum disulfide (MoS2) crystals, revealing the nature of switching mechanism in MoS2 transistors. On investigating transistor behavior as contact length changes, we find that the contact resistivity for metal/MoS2 junctions is defined by contact area instead of contact width. The minimum gate dependent transfer length is ∼0.63 μm in the on-state for metal (Ti) contacted single-layer MoS2. These results reveal that MoS2 transistors are Schottky barrier transistors, where the on/off states are switched by the tuning of the Schottky barriers at contacts. The effective barrier heights for source and drain barriers are primarily controlled by gate and drain biases, respectively. We discuss the drain induced barrier narrowing effect for short channel devices, which may reduce the influence of large contact resistance for MoS2 Schottky barrier transistors at the channel length scaling limit.

251 citations

Journal ArticleDOI
TL;DR: In this article, a 2D analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs).
Abstract: A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.

247 citations


Network Information
Related Topics (5)
Transistor
138K papers, 1.4M citations
93% related
Silicon
196K papers, 3M citations
84% related
Capacitor
166.6K papers, 1.4M citations
83% related
Thin film
275.5K papers, 4.5M citations
82% related
Voltage
296.3K papers, 1.7M citations
81% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202330
202279
202161
202055
201958
201845