Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Transistor having reduced channel dopant fluctuation

Abstract: According to one exemplary embodiment, a transistor includes a source and a drain separated by a channel. The transistor further includes a gate dielectric layer situated over the channel. The channel is situated in a well formed in a substrate. A pocket implant is not formed between the source and the drain so as to reduce dopant fluctuation in the channel, thereby reducing transistor mismatch. According to this exemplary embodiment, an LDD implant is not formed between the source and the drain so as to further reduce the dopant fluctuation in the channel.

Insulated gate semiconductor device and method of manufacturing the same

Abstract: Dot-pattern-like impurity regions are artificially and locally formed in a channel forming region. The impurity regions restrain the expansion of a drain side depletion layer toward the channel forming region to prevent the short channel effect. The impurity regions allow a channel width W to be substantially fined, and the resultant narrow channel effect releases the lowering of a threshold value voltage which is caused by the short channel effect.

Nonvolatile semiconductor memory circuit with high speed read-out

Abstract: A memory cell transistor includes a semiconductor substrate, a N-type source region, a N-type drain region, a control gate and a P+ -type emitter region, which is formed in the surface region of the drain region. An insulating film overlies the source region, the drain region, the emitter region, and the control gate. A contact hole is formed in the insulating film so that the surface of the emitter region is exposed. An emitter electrode is formed in and around the contact hole. A PNP vertical bipolar transistor is constituted by the semiconductor substrate serving as a collector region, a P+ -type buried layer serving as a collector contact, and the drain region serving as a base region.

Method of fabricating semiconductor device having high-and low-voltage MOS transistors

Abstract: A semiconductor device (76) is provided with a high-voltage portion including NMOS transistor (78) and PMOS transistor (82b) and a low-voltage portion including NMOS transistor (80) and PMOS transistor 82(a). The high-voltage NMOS transistor (78) includes source/drain regions (90a, 90b) having N- regions (90a 1 , 90b 1 ) that are self-aligned with a gate (78) and N+ regions (90a 2 , 90b 2 ) that are self-aligned with sidewall spacers (91) formed on sidewalls of the gate (78) to improve reliability under continuous high voltage operating conditions. The low voltage NMOS transistor includes source/drain regions (92a, 92b) that are self-aligned with sidewall spacers (92) to permit channel lengths to be scaled to less than 2 microns. The low-voltage PMOS transistor (82a) and high-voltage PMOS transistor (82b) include source/drain regions (116a-116d) that are self-aligned with sidewall spacer extension regions (110a) formed over sidewall spacers (91) permitting low-voltage PMOS transistor channel lengths to be scaled to less than 2 microns.

Tunnel field effect transistor with improved subthreshold swing

Abstract: The present invention provides a tunnel field effect transistor (TFET) device comprising at least following segments: - A highly doped drain region (3), - A lowly doped up to undoped channel region (2) being in contact with said drain region (3), the channel region (2) having a longitudinal direction, - A highly doped source region (1) in contact with said channel (2) region, the contact between the source region (1) and the channel region (2) forming a source-channel interface (12), - A gate dielectric (10) and a gate electrode (9) covering along the longitudinal direction at least part of the source (1) and channel (2) regions, said gate electrode (9) being situated onto said gate dielectric (10), not extending beyond said gate dielectric (10), wherein the effective gate dielectric thickness t gd,eff of the gate dielectric (10) is smaller at the source-channel interface (12) than above the channel (2) at a distance from the source-channel interface (12), the increase in effective gate dielectric thickness t gd,eff being obtained by means of at least changing the physical thickness t gd of the gate dielectric (10).