Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

EEPROM using a merged source and control gate

Abstract: A single layer of polycrystalline silicon (poly-Si) is used in an EEPROM structure, which obviates the need to form a separate control gate and floating gate. The EEPROM utilizes three separate NMOS transistors: a write transistor, a read transistor, and a sense transistor. A thin tunnel oxide layer separates the N+ source region of the write transistor from an N doped poly-Si layer and capacitively couples the source region to the poly-Si layer. The poly-Si layer extends over the N+ source region of the sense transistor and is capacitively coupled to the source region of the sense transistor via a thin gate oxide insulating layer which is thicker than the oxide layer comprising the tunnel oxide layer. This poly-Si layer continues to extend over a channel region separating the N+ source and N+ drain regions of the sense transistor, the poly-Si layer being separated from the channel via the thin gate oxide insulating layer. The drain of the sense transistor also acts as the source of the read transistor. In the above structure, the poly-Si layer acts as the floating gate over the channel of the sense transistor. Since the poly-Si floating gate is both capacitively coupled to the source of the sense transistor and to the source of the write transistor, no separate control gate or control gate electrode is needed (the source of the sense transistor acts as the control gate). The structure, inter alia, enables a higher coupling ratio during erasing, thus allowing faster erase times by coupling a higher voltage onto the poly-Si floating gate.

Brief review of the MOS device physics for low temperature electronics

Abstract: A brief review of the main physical phenomena involved in the cryogenic operation of CMOS silicon devices down to liquid helium temperature is given. Going from solid state physics towards electrical engineering point of views, several aspects such as the quantification of the inversion layer, the electronic transport in the 2D electron or hole gases, the scattering mechanisms, the impurity freeze-out in the substrate or in the lightly doped source and drain regions, the field-assisted impurity and impact ionization phenomena, the influence of series resistance and other parasitic effects (kink effect, hysteresis, transient, …) which alter the device characteristics will be discussed. The short channel effects such as drain induced barrier lowering, punch through, velocity overshoot will also be addressed.

Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 µm SOI-MOSFET

Abstract: The influence of the buried layer structure on the drain-induced barrier lowering (DIBL) is investigated for a silicon-on-insulator metal-oxide-silicon field-effect-transistor (SOI-MOSFET) by a two-dimensional device simulator. The buried layer thickness and the dielectric constant of the buried layer are varied systematically. It is found that the degradation on the threshold voltage can be separated into two components. One component originates from the electric flux via the SOI layer and the other via the buried layer. The buried insulator engineering which controls the thickness and the dielectric constant of the buried layer is effective in reducing the latter component. The gate length limit can be reduced by 23% by the buried air gap structure where the dielectric constant of the buried layer is 1.0.

Threshold voltage control of bottom-contact n-channel organic thin-film transistors using modified drain/source electrodes

Abstract: Bottom-contact n-channel C60 thin-film transistors (TFTs) with drain/source electrodes modified by benzenethiol derivatives have been fabricated to investigate the influence of the modification on the transistor characteristics. Modification using methylbenzenethiol, aminobenzenethiol, and (dimethylamino)benzenethiol having electron-donating groups causes threshold voltages to shift to low voltages. In addition, the modification provides no significant decrease in saturation mobilities. A C60 TFT with (dimethylamino)benzenethiol-modified electrodes has a low threshold voltage of 5.1 V as compared to that of 16.8 V for a TFT with nonmodified electrodes. The threshold-voltage shift is probably because the modification reduces electron-injection barrier height and improves electron injection into organic semiconductors.

Low dropout voltage regulator using a depletion pass transistor

Abstract: A linear low dropout voltage regulator is described that makes use of a depletion mode NMOS pass transistor and of a PMOS transistor in series to the NMOS transistor and connected to its drain. The depletion NMOS transistor assures low dropout operations, while the series PMOS transistor allows the current regulation even under the condition of shorted load. The same PMOS transistor may be used to disable the current in the load without generating a negative voltage at the gate of the depletion pass transistor. This regulator is inherently stable without the need for an output capacitor in parallel to the load.