Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

High voltage MOS transistor with up-retro well

Abstract: A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The implanted dopants diffuse into the epitaxial layer from the substrate during the formation of the epitaxial layer and subsequent heating steps. The implanted dopants increase the doping concentration in a lower portion of the epitaxial layer. The implanted dopants may diffuse father into the epitaxial layer than dopants in the buried layer forming an up-retro well that prevents vertical punch-through at high operating voltages for thin epitaxial layers. In addition, the doping concentration below the gate may be light so that the threshold voltage of the transistor is low. Also, the high voltage transistor of the present invention may be isolated from the substrate and the buried layer, and have symmetrical source and drain regions so that it can be used as a pass transistor.

Lighting control circuit for vehicle lamps

Abstract: The supply of a predetermined current to LEDs is controlled by using series regulators. In accordance with the controlled states of the series regulators, a switching regulator adjusts an output voltage relative to the LEDs to the maximum voltage. When a ground fault occurs at the anode of one of the LEDs, and when a short circuit occurs at the output terminal of the switching regulator and the output voltage drops abnormally, the operation of the switching regulator is halted. When the gate voltage of an NMOS transistor is raised due to the disconnection of one of the LEDs, or when the drain voltage of the transistor is raised due to a short circuit at one of the LEDs, a Zener diode becomes conductive and an NPN transistor and a PNP transistor are rendered on. Then, a current flows through a diode, and as the gate voltage has been lowered, the operation of the NMOS transistor is halted, so that the remaining, normal LEDs are protected when an abnormality occurs.

NOR flash memory cell with high storage density

Abstract: Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A sourceline is formed in a trench adjacent to the vertical floating gate transistor and coupled to the first source/drain region. A transmission line coupled to the second source/drain region. And, a wordline is coupled to the control gate perpendicular to the sourceline.

Performance advantage of Schottky source/drain in ultrathin-body silicon-on-insulator and dual-gate CMOS

Abstract: Here, for the first time, advanced simulation models are used to investigate the performance advantage of Schottky source/drain ultrathin-silicon technologies at a 25-nm gate length target. Schottky and doped source/drain MOSFETs were optimized and compared using a novel benchmark. Mixed-mode simulations of optimized devices in a two-stage NAND chain show an approximate 45% speed advantage of Schottky source/drain for one set of parameter choices. Contact requirements for Schottky source/drain, and for doped source/drain relative to ITRS targets through 2016, are discussed.

Drain avalanche breakdown in gallium arsenide MESFET's

Abstract: Avalanche breakdown in GaAs MESFET's simulated by two-dimensional (2-D) numerical calculation with a two-carrier model. The simulation involves electron-hole pair generation due to impact ionization and employs a simplified model of the surface depletion layer of GaAs. Gate-bias-dependent drain breakdown voltage is demonstrated. The effect of the surface depletion layer, drain-to-gate spacing and n/sup +/ layer under the drain contact upon the breakdown voltage is demonstrated. It is clarified that the surface depletion layer has a pronounced effect on the gate-bias dependence of the breakdown voltage. The breakdown mechanism is explained in terms of conductivity modulation in the semi-insulting substrate. >