Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide

Abstract: A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region This higher-doped pocket of semiconductor material does not totally deplete during device operation Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region

The Ground Plane in Buried Oxide for Controlling Short-Channel Effects in Nanoscale SOI MOSFETs

Abstract: The ground plane (GP) concept is one of the techniques used to reduce the drain-induced barrier lowering (DIBL) in nanoscale MOSFETs and is effective only when the distance between the GP and the drain is small as compared with the channel length. Therefore, if the GP is placed in the substrate (GPS), the buried oxide (BOX) thickness should be kept as small as possible which, however, results in an increased subthreshold slope. As a result, for sub-100-nm channel lengths, it is not possible to achieve both reduced DIBL and steep subthreshold slope using GPS. In this brief, a new device structure with the GP BOX is proposed to overcome the aforementioned shortcomings so that a reduced DIBL as well as an improved subthreshold slope can be obtained. Two-dimensional simulation is used to understand the efficacy of the proposed method.

Fabrication process for EEPROMS with high voltage transistors

Abstract: A CMOS fabrication process for EEPROMs having high-breakdown-voltage peripheral transistors in which a single implant step early in the process forms buried implants for both the memory cell's tunnel area source and the high voltage transistor's source and drain areas. The single implant step can be formed either before or after the formation of the channel stops and field oxide around the devices. The floating gate of the memory cell and the gates of the other devices are formed with polysilicon, the gates of the high voltage transistor overlapping the buried implants of its source and drain. The sources and drains of the other peripheral devices are then formed, using their polysilicon gates as a self-aligning mask. This may also include the formation of contact source and drain for the high voltage transistor. The process concludes with the formation of one or two layers of conductive lines connecting to specified drains, sources and gates to form a desired circuit pattern.

UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime

Abstract: In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Based on experimental devices, both n- and p-type GP configurations are considered and compared with standard no-GP substrates. In a standard single-gate (SG) regime, the effect of GP implementation on analog FoM (related to slightly higher body factor and improved gate-to-channel coupling) is negligible. Moreover, p-GP implementation allows higher intrinsic gain at high frequency compared with no-GP and n-GP substrates. Furthermore, we demonstrate that application of an asymmetric double-gate (ADG) (i.e. front-gate to back-gate/substrate connection) regime allows better control of short-channel effects in terms of drain induced barrier lowering, subthreshold slope and threshold voltage control, due to improved gate(s)-to-channel coupling. Application of an ADG mode is shown to enhance analog FoM such as transconductance, drive current and intrinsic gain of UTBB SOI MOSFETs. Finally, simulations predict that improvements of analog FoM provided by ADG mode can be obtained in the whole dynamic operation range. Moreover, ADG mode provides elimination of the high-frequency substrate coupling effects.

Field effect transistor with short channel and manufacturing method therefor

Abstract: On a p-type semiconductor substrate (well region) there are arranged apart from each other an n-type source region and an n-type drain region, a channel region therebetween, and a gate electrode. A pair of p-type channel diffusion regions doped more heavily than the substrate are formed along the channel boundary between the source region and the drain region and the substrate. The channel diffusion region below the drain region is doped with an n-type impurity to achieve a lower active impurity concentration relative to that in the channel diffusion region below the gate electrode.