Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Gate-Length and Drain-Bias Dependence of Band-to-Band Tunneling-Induced Drain Leakage in Irradiated Fully Depleted SOI Devices

Abstract: The effects of gate length and drain bias on the off-state drain leakage current of irradiated fully-depleted SOI n-channel MOSFETs are reported. The experimental results are interpreted using a model based on the combined effects of band-to-band tunneling (BBT) and the trapped charge in the buried oxide. For negative gate-source voltages, the drain leakage current increases with the drain voltage because the electric field in the gate-to-drain overlap region is increasing. The off-state current in these devices increases with total ionizing dose due to oxide trapped charge build up in the buried oxide, enhanced by the BBT mechanism. The experimental data show that these effects are more significant for devices with shorter gate-lengths. Simulation results suggest that the BBT-generated holes are more likely to drift all the way from the drain to the source in shorter devices, enhancing the drain leakage current, while they tend to tunnel across the gate oxide in longer devices.

On Backscattering and Mobility in Nanoscale Silicon MOSFETs

Abstract: The DC current-voltage characteristics of an n-channel silicon MOSFET with an effective gate length of about 60 nm are analyzed and interpreted in terms of scattering theory. The experimental results are found to be consistent with the predictions of scattering theory - the drain current is closer to the ballistic limit under high drain bias than under low drain bias, and the on-current in strong inversion is limited by a small portion of the channel near the source. The question of how the low- and high- V DS drain currents are related to the near-equilibrium, long-channel mobility is also addressed. In the process of this analysis, theoretical and experimental uncertainties that make it difficult to extract numerically precise values of the scattering parameters are identified.

Hot Carrier Effects in Low-Temperature Polysilicon Thin-Film Transistors

Abstract: We have studied the reliability of a low-temperature polysilicon (poly-Si) thin-film transistor (TFT). The drain avalanche hot electron effect was characterized by changing the stress gate and drain voltage dependence. Generation of hot carriers was confirmed using an emission microscope. It was found that the degradation was improved by the lightly doped drain (LDD) structure. A degradation model was proposed and analyzed along with a two-dimensional device simulator. Reasonable agreement with the experimental results was successfully obtained. It was found that the density of state (DOS) of poly-Si was increased by the hot carrier effect locally around the drain region.

Forming abrupt source drain metal gate transistors

Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.

Bias Stress Induced Threshold Voltage Shift in Pentacene Thin-Film Transistors

Abstract: Threshold voltage instabilities in SiO2/polyimide dual-gate dielectric pentacene thin-film transistors are investigated as a function of bias stress time for 1000 s at temperatures between 260 and 340 K in nitrogen atmosphere. Field-effect mobility maintains constant values at every measurement temperature during the application of constant bias stress voltage. The threshold voltage shift at all measurement temperatures is described by the stretched exponential stress time dependence of ΔVth(t) = ΔVth0{1-exp [-(t/τ)β]}. These experimental results suggest that our threshold voltage shift can be interpreted as carrier injection from the pentacene channel into traps located at the channel/gate dielectric interface.