Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Semiconductor on insulator transistor

Abstract: The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabricated. The channel transistor has opposite conductivity type to the transistor using the main channel region. The source of the channel transistor is connected to the channel and the drain of the channel transistor is connected to a reference voltage. The same gate is used to control the channel transistor and the main transistor. When a voltage which causes the main transistor to be on is applied, the channel transistor is off, thus allowing the channel to float and allowing higher drive current. On the other hand, when a voltage to turn off the main transistor is applied, the channel transistor is turned on, thus clamping the channel region to the reference voltage. This allows for consistent threshold voltage control of the main transistor.

Low leakage current offset-gate thin film transistor structure

Abstract: A thin film transistor structure and methods of manufacture provide high ON/OFF current ratio and significantly reduce OFF state leakage currents. A doped thin film disposed on an insulating substrate is etched to form opposing source and drain regions. An undoped thin film is disposed between the opposing source and drain regions so that there is some overlap of the undoped thin film onto the top sides of the source and drain regions. Conventional photomasking, etching and ion implantation steps are then used to form a gate electrode offset from at least the drain region, and preferably offset from both source and drain regions, as well as conventional insulation and interconnect layers. The reduction in electric field intensity in the drain region, and the reduction in trap state density result from, performing heavy junction doping prior to deposition of the undoped thin film, and offsetting the gate electrode from the drain region. This structure provides very low OFF state leakage current while not seriously affecting the ON current. Several alternative fabrication processes are disclosed.

Optimization of nonplanar power MOS transistors

Abstract: Analysis of fundamental MOSFET parameters predicts device limits in high-voltage high-speed operation that exceed the performance of bipolar devices. The optimization of voltage, speed, and "on" resistance parameters for power MOSFET's suggests a vertical three-terminal device design with short, wide channels; a wide, lightly doped drain region; and field terminator rings at the device perimeter. Utilizing this design philosophy, VMOS transistors have been produced with source-drain breakdown voltage greater than 450 V, and 5.5-Ω "on" resistance for 2.0-mm2active area. With a high channel width packing density design and 2.5-mm2active area, a 30-V transistor has also been produced having only 0.060-Ω "on" resistance. The breakdown voltage and "on" resistance of these devices exceed the performance of other power MOSFET's currently available. Also, the switching speed of these devices (better than 15 ns) far exceeds the performance of high-voltage bipolar transistors. Measurements of drain leakage current at 200-V drain potential show a resistance ratio R_{off}/R_{on} of approximately 1010for a 20-V variation in gate-to-source voltage.

Nonvolatile memory and method of making same

Abstract: A method of discharging a charge storage location of a transistor of a non-volatile memory includes applying first and second voltages to a control gate and a well region, respectively, of the transistor. The first voltage is applied to the control gate of the transistor, wherein the control gate has at least a portion located adjacent to a select gate of the transistor. The transistor includes a charge storage location having nanoclusters disposed within dielectric material of a structure of the transistor located below the control gate. Lastly, a second voltage is applied to the well region located below the control gate. Applying the first voltage and the second voltage generates a voltage differential across the structure for discharging electrons from the nanoclusters of the charge storage location.

Computer analysis of punch-through in MOSFETs

Abstract: A two-dimensional numerical analysis is made for MOSFETs having short channel lengths. The short channel MOSFET is especially characterized by the existence of the punch-through current which cannot be explained by the one-dimensional MOSFET models. The two-dimensional analysis makes clear the following facts relating about the punch-through mechanism. The punch-through is a condition in which the depletion layers of the source and the drain connect mutually at the deep region in the substrate even in equilibrium. The punch-through current is injected through the saddle point of the intrinsic potential into the drain region by the electric field from the drain, at the low gate voltages.