Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Negative Capacitance Field Effect Transistor With Hysteresis-Free Sub-60-mV/Decade Switching

Abstract: We demonstrate a nearly hysteresis-free sub-60-mV/decade subthreshold swing (SS) operation in a p-type bulk metal–oxide–semiconductor field-effect transistor externally connected to a ferroelectric capacitor. The SS $\mu \text{m}\sim 10$ nA/ $\mu \text{m}$ of drain current) and at large drain current levels. However, the extent of hysteresis is found to be strongly dependent on the drain voltage. At high drain voltages, large hysteresis occurs, indicating the influence of drain voltage in the charge balance with the ferroelectric capacitor.

Current/voltage characteristic collapse in AlGaN/GaN heterostructure insulated gate field effect transistors at high drain bias

Abstract: The authors describe the current/voltage characteristic collapse under a high drain bias in AlGaN/GaN heterostructure insulated gate field effect transistors (HIGFETs) grown on sapphire substrates. These devices exhibit a low resistance state and a high resistance state, before and after the application of a high drain voltage, respectively. At room temperature, the high resistance state persists for several seconds. The device can also be returned into the low resistance state by exposing it to optical radiation. Electron trapping in the gate insulator near the drain edge of the gate is a possible mechanism for this effect, which is similar to what has been observed in AlGaAs/GaAs HFETs at cryogenic temperatures.

Extracting Parameters from the Current–Voltage Characteristics of Organic Field‐Effect Transistors

Abstract: Organic field-effect transistors were fabricated with vapor-deposited pentacene on aluminum oxide insulating layers. Several methods are used in order to extract the mobility and threshold voltage from the transfer characteristic of the devices. In all cases, the mobility is found to depend on the gate voltage. The first method consists of deriving the drain current as a function of gate voltage (transconductance), leading to the so-called field-effect mobility. In the second method, we assume a power-law dependence of the mobility with gate voltage together with a constant contact resistance. The third method is the so-called transfer line method, in which several devices with various channel length are used. It is shown that the mobility is significantly enhanced by modifying the aluminum oxide layer with carboxylic acid self-assembled monolayers prior to pentacene deposition. The methods used to extract parameters yield threshold voltages with an absolute value of less than 2 V. It is also shown that there is a shift of the threshold voltage after modification of the aluminum oxide layer. These features seem to confirm the validity of the parameter-extraction methods.

Low voltage EEPROM/NVRAM transistors and making method

Abstract: A new FET device configuration for electrically programmable memories (EPROM), flash/electrically erasable and programmable read-only memories (EEPROM), and non-volatile Random Access Memory (NVRAM) which adds vertical components to a previously planar floating gate cell structure; efficiency of electron injection from the channel to floating gate is enhanced by many orders of magnitude because electrons accelerated in the channel penetraite in the direction of movement, straight into the floating gate. The floating gate resides over a series of arbitrary horizontal and vertical channel region components, the key topological feature being that the vertical channel resides near the drain, allowing electrons to penetrate straight into the floating gate. In contrast, the prior art relies on the indirect process of electron scattering by phonon and the 90 degree upward redirection of motion to the floating gate used by conventional Channel Hot Electron EPROM and EEPROM cells. With the feature of the vertical injection step, high injection efficiency can be achieved at much lower operating voltages, and program time is decreased, which has been a limiting factor in EEPROM applications. Operation at lower voltages improves reliability and overall process complexity. The feature of high injection efficiency at low drain voltage also makes multi-level storage easier and more controllable since the storage of electrons can be controlled by a single control gate voltage. This high efficiency, low voltage, step channel enables a single polysilicon EPROM transistor. Also, a double polysilicon EEPROM transistor with the vertical injection step near drain can achieve erase capability of polysilicon to polysilicon, something that could only be practically built with a triple polysilicon EEPROM cell, in prior art. This combination of a low voltage program and poly to poly erase in a double polysilicon split gate cell with the vertical injection step achieves the non-volatile RAM feature of write 0 (program) or 1 (erase) for a selected word line (control gate) at once. Fabrication methods for the vertical injection step channel near drain are also be described.

Split-channel antifuse array architecture

Abstract: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor. More specifically, the present invention provides an effective method for utilizing split channel MOS structures as an anti-fuse cell suitable for OTP memories.