Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Novel Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels

Abstract: The novel gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with multiple nanowire channels (MNCs) have been, for the first time, fabricated using a simple process to demonstrate high-performance electrical characteristics and high immunity to short-channel effects (SCEs). The nanowire channel with high body-thickness-to-width ratio (TFin/WFin), which is approximately equal to one, was realized only with a sidewall-spacer formation. Moreover, the unique suspending MNCs were also achieved to build the GAA structure. The resultant GAA-MNC TFTs showed outstanding three-dimensional (3-D) gate controllability and excellent electrical characteristics, which revealed a high on/off current ratio ( > 108), a low threshold voltage, a steep subthreshold swing, a near-free drain-induced barrier lowering, as well as an excellent SCE suppression. Therefore, such high-performance GAA-MNC TFTs are very suitable for applications in system-on-panel and 3-D circuits.

A first-order theory of the static induction transistor

Abstract: A first-order theory of the static induction transistor (SIT) is proposed, which provides a unitary analytical description of its characteristics over the full range of normally encountered biasing conditions. The blocking-state and low-current analysis is based on the original modeling device of considering the intrinsic region of the SIT biased, across its boundary to the drain, by a cosine potential, the maximum value of which is set by a virtual intrinsic-drain electrode. The analytical development leads to design equations for specific SIT parameters such as barrier height, gate efficiency, voltage gain factor and forward blocking gain. The predicted low-current I - V characteristics are consistent with the reported experimental ones. Numerical over-relaxation calculations have been used for a spot-check verification of the analytical model, as well as for extracting the pertinent parameters of the extrinsic region. The intermediate- and high-current analysis of the intrinsic device reveals an interesting electrostatic feedback from the electronic charge in the channel, which carries the drain current, to the potential barrier which controls this current, resulting in triode-like I - V characteristics. The current flows within the limits of a neutral effective channel, which extends from the channel axis to the gates, as the drain current increases. This sets a drain current limitation for the linear range, corresponding to the situation when the channel is completely and uniformly filled with electrons, at the level of its doping concentration. The full-range I - V characteristic of the SIT is basically of the form i + ln i = v , where i and v are normalized drain current and equivalent gate voltage, respectively.

Si/SiGe MOSFET and method for fabricating the same

Abstract: The present invention relates to a metal silicon field effect transistor (MOSFET), and more particularly to a MOSFET, using a Si or SiGe channel to effectively adjust threshold voltage. The transistor according to the present invention can solve the problems, such as the punch-through caused by the short distance between the source region and the drain region, the decrease of the breakdown voltage between the source region and the drain region and the leakage current flowing into the bulk region beneath the channel due to the drain-induced barrier lowering. Furthermore, because the source region and the drain region are isolated from the semiconductor substrate by the lower insulation layer, the removal of the parasite junction capacitor speed up the transistor.

Structure and method of manufacture for MOS field effect transistor having lightly doped drain and source diffusion regions

Abstract: Structures and methods of manufacture are described for a MOS FET that is suitable for extreme miniaturization, of a type in which lightly doped drain and source diffusion regions are formed respectively adjoining the conventional highly doped drain and source diffusion regions in the semiconductor substrate surface, for reducing electric field concentration in the drain region. The underside of the gate electrode of the FET is formed with a downwardly protruding convex shape, so that a thick region of gate insulation film is positioned between the drain diffusion regions and the most closely adjacent part of the gate electrode, whereby gate-to-drain stray capacitance and the vertical component of electric field within the lightly doped drain diffusion region are reduced. The underside of the gate electrode can be formed in the required shape by various methods which effectively utilize self alignment and are easily adapted to currently used types of LSI manufacturing process.