Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Impact of a Pocket Doping on the Device Performance of a Schottky Tunneling Field-Effect Transistor

Abstract: It is known that a pocket at the drain end of a Schottky barrier tunneling FET (SB-TFET) helps to improve the device performance in terms of greatly suppressed ambipolar current and reduced drain-induced barrier lowering (DIBL) A detailed investigation, with the help of a numerical device simulator, of the impact of using such a pocket either at the source end or at both the source and the drain ends of an SB-TFET is reported for the first time in this paper The performance of the above-mentioned two devices is compared with a device having a pocket at the drain end and a conventional MOSFET Optimization of the barrier height and the pocket parameters is made before performance comparison It is observed that a pocket at the drain end helps suppress the ambipolar current and reduce both the subthreshold swing and the DIBL On the other hand, a pocket at the source end helps to improve the ON-state current \(I_{\mathrm{{\scriptstyle ON}}}\) Using a pocket at both the source and the drain ends results in overall improvement of the device performance The effects of scaling on such device performance parameters are also reported

Impact of $\hbox{Al}_{2}\hbox{O}_{3}$ Passivation Thickness in Highly Scaled GaN HEMTs

Abstract: This letter studies the influence of the passivation thickness on the device characteristics of InAlGaN/GaN high-electron-mobility transistors with a gate length between sub-30 and 70 nm. As the Al2O3 passivation thickness increases, the current collapse in 80-μs pulsed-I -V measurements decreases from 30% to 13%, while dc characteristics are almost unchanged with the exception of increasing drain-induced barrier lowering. The thicker passivation increases the fringing gate capacitance, which can be about 30% of the total gate capacitance in the devices with a gate length below 35 nm. This capacitance results in a significant drop of current-gain cutoff frequency (fT), and its effect is more important in the shorter gate length devices.

Threshold Voltage Model for Deep-Submicrometer MOSFET's

Abstract: Based on analysis on short-channel effect and drain induced barrier lowering (DIBL) effect, a threshold voltage model for high-k MOSFET's is etablished by introducing a coefficient that interrelates the two effects. Influences of various factors on threshold voltage shift are simulated and investigated, and the optimal range of k values is obtained.

Mosfet with recessed channel film and abrupt junctions

Abstract: MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.

High power semiconductor electronic components with increased reliability

Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.