Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

A 600-volt MOSFET designed for low on-resistance

Abstract: A 600-V vertical power MOSFET with low on-resistance is described. The low resistance is achieved by means of achieving near-ideal drain junction breakdown voltage and reduced drain spreading resistance from the use of an extended channel design. The various tradeoffs inherent in the design are discussed. Both calculated and experimental data are presented. The remote source configuration of the experimental device is also discussed.

A novel 50 nm vertical MOSFET with a dielectric pocket

Abstract: A vertical metal-oxide-semiconductor field-effect transistor with the novel feature of a dielectric pocket between the channel and source/drain has been fabricated and tested. These dielectric pocket vertical MOSFETs (DPV-MOSFETs) show an improved suppression of short-channel effects such as VT roll-off and drain induced barrier lowering (DIBL). This is due to reduced charge sharing, thus allowing better threshold voltage control. The dielectric pocket also prevents dopant diffusion from the source/drains into the body during device fabrication, mitigating bulk punchthrough.

Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device

Abstract: In the fabrication of a metal oxide semiconductor field effect transistor (MOSFET) or of a metal gate field effect transistor (MESFET), characterized by a polycrystalline silicon gate (13) and a short channel of about a micron or less, a sequence of steps is used involving the simultaneous formation of source, drain, and gate electrode contacts by a bombardment with a transition metal, such as platinum, which forms metal-silicide layers (19, 21, 18) on the source and drain regions (10.1, 10.2) as well as the silicon gate electrode (13).

Flash EPROM cell and method of making such cell

Abstract: A flash EPROM cell is fabricated using a two polysilicon enhancement mode n-channel transistor process. An active transistor region is formed in a silicon substrate (14) by growing a field oxide (16) around the region. A first polysilicon layer is deposited, etched, and oxidised to form an insulated control gate electrode (18). A second polysilicon layer is deposited over the active transistor region and the control gate electrode (18) and then anisotropically etched to remove all of the second polysilicon material except for a filament (20) adjacent to the control gate electrode (18), which forms a floating gate electrode (20). Source and drain regions (10, 12) are formed in the active transistor region with the control gate electrode (18) and the floating gate electrode (20) positioned over the channel region interconnecting the source and drain regions. The cell is programmed by hot electron channel current injection by proper voltage biasing of the control gate electrode (18) and drain (12). The cell can be either symmetrical or asymmetrical depending on the configuration of the floating gate filament electrode (20).

Field effect transistor having impurity regions of different depths and manufacturing method thereof

Abstract: Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.